ISL88017 Intersil Corporation, ISL88017 Datasheet - Page 5

• Manufacturer Part Number: ISL88017
• Description: (ISL88016 / ISL88017) 6-Pin Voltage Supervisors
• Manufacturer: Intersil Corporation

Principles of Operation
The ISL88016 and ISL88017 devices provides a low cost
solution for those voltage monitoring applications needing
supply voltage supervision with power reset control, and
manual reset assertion. By integrating these common
features along with three pins of Vth programming into a
small 6 Ld TSOT-23 package and using only 1µA of supply
current, the ISL88016 and ISL88017 devices can lower
system cost, reduce board space requirements, and
increase the reliability of a system while reducing inventory
overhead costs.
Low Voltage Monitoring
During normal operation, the ISL88016 and ISL88017
monitor the voltage level of V
(RST = LOW) if this voltage is less than the programmed
voltage trip point. The reset signal prevents system
operation during a power failure or brownout condition. This
reset signal remains asserted until V
threshold setting for the reset time delay period t
Figure 1).
The ISL88016 and ISL88017 allow users to customize the
Power-On Reset voltage threshold level, which is the voltage
at which the reset is deasserted. The three VSET inputs are
either tied to V
the Power-On Reset Voltage Setting table on page 3 for
specific voltage configuration. Also see Figure 2 for a
schematic representation of the VSET pins being
programmed, noting the minimum necessary components
for IC operation. Do not attempt to reprogram a V
the IC is biased.
V
DD
DD
MR
RST
, GND or left open to program V
V
1V
TH /
V
POR
DD
5
. The device asserts a reset
t
POR
DD
FIGURE 1. VOLTAGE MONITORING TIMING DIAGRAM
exceeds the voltage
POR
t
TH
TH
RST
ISL88016, ISL88017
. See
while
. (See
t
POR
Power-On Reset (POR)
Applying power to the ISL88016 and ISL88017 activates a
POR circuit which asserts reset once V
goes LOW). This provides several benefits:
• It prevents the system microprocessor from starting to
• It prevents the processor from operating prior to
• It ensures that the monitored device is held out of
• It allows time for an FPGA to download its configuration
The reset signal remains asserted until V
minimum voltage sense level for time period t
ensures that the V
Optional V
transients if needed.
operate with insufficient voltage.
stabilization of the oscillator.
operation until internal registers are properly loaded.
prior to initialization of the circuit.
FIGURE 2. SETTING V
DD
de-coupling capacitance can be added to filter
RST/MR
VSET1
DD
GND
voltage has stabilized.
ISL88016
ISL88017
POR
USING VSET INPUTS
>t
MR
V
VSET3
VSET2
DD
DD
t
POR
DD
= 1 V. (i.e., RST
rises above the
POR
December 22, 2006
. This
FN6141.0