AD607 Analog Devices, AD607 Datasheet
AD607
Available stocks
Related parts for AD607
AD607 Summary of contents
Page 1
... GSM, CDMA, TDMA, and TETRA Receivers Satellite Terminals Battery-Powered Communications Receivers GENERAL DESCRIPTION The AD607 low power receiver IF subsystem for opera- tion at input frequencies as high as 500 MHz and IFs from 400 kHz to 12 MHz. It consists of a mixer, IF amplifiers, I and Q demodulators, a phase-locked quadrature oscillator, AGC detector, and a biasing system with external power-down. The AD607’ ...
Page 2
... Sine Wave Input, Baseband Output From FDIN to VMID Sine Wave Input at Pin 10.7 MHz For Power Up on Logical High To PLL Locked Midgain 10.7 MHz Operation to 2.7 V Minimum Supply Voltage Operation to 4.5 V Minimum Supply Voltage –2– AD607ARS Min Typ Max Units 500 MHz 54 mV –15 dBm – ...
Page 3
... ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD607 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality ...
Page 4
... Supply to mixer, low level IF, PLL, and gain control. PIN CONNECTION 20-Pin SSOP (RS-20) FDIN 1 20 VPS1 COM1 2 19 FLTR PRUP 3 18 IOUT LOIP 4 17 QOUT RFLO 5 AD607 16 VPS2 TOP VIEW RFHI 6 15 DMIP (Not to Scale) GREF 7 14 IFOP 8 MXOP 13 COM2 9 12 VMID GAIN/RS ...
Page 5
... S0 NOISE SOURCE HP8656B RF_OUT IEEE SYNTHESIZER HP6633A VPOS VNEG IEEE SPOS SNEG DCPS DP8200 VPOS VNEG IEEE SPOS SNEG V REF REV. 0 Typical Performance Characteristics–AD607 HP8764B CHARACTERIZATION BOARD 1 V RFHI MXOP LOIP P6205 IFOP IFHI X10 FET PROBE ...
Page 6
... AD607 HP346B 28V NOISE NOISE SOURCE HP6633A VPOS VNEG IEEE SPOS SNEG DCPS DP8200 VPOS VNEG IEEE SPOS SNEG V REF HP8764B 50 0 HP8656B RF_OUT IEEE SYNTHESIZER HP3326A DCFM OUTPUT_1 IEEE OUTPUT_2 DUAL SYNTHESIZER HP6633A VPOS VNEG IEEE SPOS ...
Page 7
... BOARD RFHI LOIP IFHI DMIP FDIN PLL VPOS R1 BIAS 10k PRUP HI GAIN LO I Figure 7. Power-Up Threshold Test Set –7– AD607 CHARACTERIZATION BOARD RFHI MXOP LOIP IFHI IFOP DMIP IOUT FDIN PLL QOUT VPOS BIAS PRUP GAIN CHARACTERIZATION BOARD ...
Page 8
... AD607 FL6082A RF_OUT IEEE MOD_OUT HP6633A VPOS VNEG IEEE SPOS SNEG DCPS DP8200 VPOS VNEG IEEE SPOS SNEG V REF HP8112 IEEE PULSE_OUT PULSE GENERATOR HP8656B IEEE RF_OUT SYNTHESIZER HP6633A VPOS VNEG IEEE SPOS SNEG DCPS FL6082A RF_OUT IEEE MOD_OUT HP6633A VPOS ...
Page 9
... RFHI DMIP C9 1nF 7 GREF IFOP 8 MXOP COM2 R13 9 VMID GAIN 301 10 IFHI IFLO 51.1 332 1nF Figure 12. AD607 Characterization Board –9– AD607 1103 IN1 OUT1 HP8765B 0 HP8694E 1 C IN2 OUT2 RF_IN IEEE SPEC AN PROBE SUPPLY 0.1µ ...
Page 10
... AD607 VPOS = 5V MHz 15 VPOS = 3V MHz VPOS = 5V MHz VPOS = 3V MHz 110 130 150 170 RF FREQUENCY – MHz Figure 13. Mixer Noise Figure vs. Frequency 4500 4000 3500 C SHUNT COMPONENT 3000 2500 2000 1500 R SHUNT COMPONENT ...
Page 11
... MIXER –4 –6 –8 –10 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 GAIN VOLTAGE – Volts Figure 20. AD607 Gain Error vs. Gain Control Voltage, Representative Part 996.200 µs 1.00870 ms Timebase = 2.5 µs/div Delay = 1.00870 ms Memory 1 = 100.0 mVolts/div Offset = 127.3 mVolts Timebase = 2.50 µs/div Delay = 1.00870 ms Memory 2 = 20.00 mVolts/div Offset = 155.2 mVolts Timebase = 2.50 µ ...
Page 12
... AD607 –2 – GAIN BALANCE – dB Figure 25. Demodulator Gain Balance, Histogram +25 C, VPOS = 10.7 MHz I_GAIN_CORR 16 15 QUADRATIC FIT OF I_GAIN_CORR (IFF 0.2 0.4 0.6 0.8 1.0 1.2 BASEBAND FREQUENCY – MHz Figure 26. Demodulator Gain vs. Frequency 20 19 I_GAIN_CORR 18 17 ...
Page 13
... P be assumed Figure 33 shows the main sections of the AD607. It consists of a variable-gain UHF mixer and linear four-stage IF strip, which together provide a voltage controlled gain range of more than 90 dB; followed by dual demodulators, each comprising a multi- plier followed by a 2-pole, 2 MHz low-pass filter ...
Page 14
... IF amplifier’s linear range. IF Amplifier Most of the gain in the AD607 arises in the IF amplifier strip, which comprises four stages. The first three are fully differential and each has a gain span for the nominal AGC voltage range. Thus, in conjunction with the mixer’ ...
Page 15
... T high absolute accuracy AD607 GAIN/RSSI Figure 38. Interfacing the AD607 to the AD7013 or AD7015 Baseband Converters R T I/Q Demodulators Both demodulators (I and Q) receive their inputs at pin DMIP. Internally, this single-sided input is actually differential; the noninverting input is referenced to pin VMID. Each demodula- ...
Page 16
... FDIN. When this signal is at the IF, inphase and quadrature baseband out- puts are generated at IOUT and QOUT, respectively. The Table II. AD607 Gain and Manual Gain Control Voltage vs. Power Supply Voltage Power Supply GREF Voltage ...
Page 17
... Gain Distribution As in all receivers, the most critical decisions in effectively using AD607 the AD607 relate to the partitioning of gain between the various FDIN subsections (Mixer, IF Amplifier, Demodulators) and the place- ment of filters achieve the highest overall signal-to- noise ratio and lowest intermodulation distortion. ...
Page 18
... NORMAL OPERATING RANGE Figure 44. Gain Distribution for GREF = 1.23 V Using the Internal AGC Detector The AD607 includes a detector cell at the output of the IF am- plifier that allows it to provide its own AGC and output-leveling function in receiver applications where DSP support is not needed only necessary to connect a filter capacitor between the GAIN pin and ground to invoke this feature ...
Page 19
... In some applications, even slower AGC may be desired than that required to prevent modulation tracking. AD607 EVALUATION BOARD The AD607 evaluation board (Figures 46 and 47) consists of an AD607, ground plane, I/O connectors, and a 10.7 MHz band- pass filter. The RF and LO ports are terminated in 50 provide a broadband match to external signal generators to al- low a choice of RF and LO input frequencies ...
Page 20
... AD607 Figure 47. Evaluation Board Layout –20– REV. 0 ...
Page 21
... The board provides SMA connectors for the RF and LO port inputs, the demodulated I and Q outputs, the manual gain con- trol (MGC) input, the PLL input, and the power-up input. In addition, the IF output is also available at an SMA connector; Table III. AD607 Evaluation Board Input and Output Connections Reference Connector Designation ...
Page 22
... SIGNAL GENERATOR 240.02 MHz IEEE CONTROLLER If the AD607’s internal AGC detector is used, then the GAIN/ RSSI (Pin 12) becomes an output and the RSSI voltage appears across C12, which serves as an integrating capacitor. This volt- age must be monitored by a high impedance (100 k minimum) probe. The internal AGC loop holds the IF voltage at IFOP (Pin 14) at 300 mV ...
Page 23
... Plastic SSOP (RS-20 0.212 (5.38) 0.205 (5.207) 0.311 (7.9) 0.301 (7.64 0.07 (1.78) 0.295 (7.50) 0.066 (1.67) 0.271 (6.90 0.0256 (0.65) 0.009 (0.229) BSC 0.005 (0.127) 1. LEAD NO. 1 IDENTIFIED BY A DOT. 2. LEADS WILL BE EITHER TIN PLATED OR SOLDER DIPPED IN ACCORDANCE WITH MIL-M-38510 REQUIREMENTS –23– AD607 0.037 (0.94) 0.022 (0.559) ...
Page 24
–24– ...