AD6641 Analog Devices, AD6641 Datasheet
AD6641
Available stocks
Related parts for AD6641
AD6641 Summary of contents
Page 1
... Analog Devices. Trademarks and registered trademarks are the property of their respective owners. GENERAL DESCRIPTION The AD6641 is a 250 MHz bandwidth digital predistortion (DPD) observation receiver that integrates a 12-bit 500 MSPS ADC, a 16k × 12 FIFO, and a multimode back end that allows ...
Page 2
... AD6641 TABLE OF CONTENTS Features .............................................................................................. 1 Applications....................................................................................... 1 General Description ......................................................................... 1 Functional Block Diagram .............................................................. 1 Revision History ............................................................................... 2 Product Highlights ........................................................................... 3 Specifications..................................................................................... 4 DC Specifications ......................................................................... 4 AC Specifications.......................................................................... 5 Digital Specifications ................................................................... 6 Switching Specifications .............................................................. 7 SPI Timing Requirements ........................................................... 8 Absolute Maximum Ratings.......................................................... 10 REVISION HISTORY 4/11—Revision 0: Initial Version Thermal Resistance .................................................................... 10 ESD Caution................................................................................ 10 ...
Page 3
... FIFO data. The data stored in the FIFO can be accessed via a SPORT, SPI, 12-bit parallel CMOS port, or 6-bit DDR LVDS interface. The maximum output throughput supported by the AD6641 is in the 12-bit CMOS or 6-bit DDR LVDS mode and is internally limited to 1/8 input sample rate. This corresponds to the maximum output data rate of 62 ...
Page 4
... Full Full −2.6 Full −6.8 Full Full Full Full Full 1.18 Full Full 25°C Full 1.8 Full 1.8 Full 1.8 Full Full Full Full Full Full Rev Page AD6641-500 Typ Max Unit 12 Bits Guaranteed 0.0 +1.8 mV −2.3 +3 ±0.5 LSB ±0.6 LSB 18 μV/°C 0.07 %/°C 1.5 1.6 V p-p 1 kΩ ...
Page 5
... Full 77 25°C 25°C 25°C 25°C Full 25°C 25°C 25°C 25°C Full 25°C 25°C 25°C 25°C Rev Page AD6641 AD6641-500 Typ Max Unit 66.0 dBFS 65.9 dBFS dBFS 65.8 dBFS 65.1 dBFS 66.0 dBFS 65.7 dBFS dBFS 65.3 dBFS 64.6 dBFS 10.7 Bits 10 ...
Page 6
... Full Full Full 0.2 Full −1.8 Full −10 Full −10 Full 8 Full Full Full DRVDD − 0.05 Full Full Full SPI_VDDIO − 0.05 Full Rev Page AD6641-500 Typ Max CMOS/LVDS/LVPECL 0.9 1.8 −0.2 +10 + CMOS 0.2 × SPI_VDDIO 0 − CMOS 0.2 × DRVDD 0 −60 ...
Page 7
... Full Twos complement, Gray code, or offset binary (default) = +85° −1.0 dBFS, full scale = 1.5 V, unless otherwise noted. MAX IN Rev Page AD6641 AD6641-500 Typ Max LVDS 454 1.375 CMOS DRGND + 0.05 AD6641-500 Temp Min Typ Max Full 62.5 Full 62.5 Full 1 Full 1 25°C 0.2 25°C ...
Page 8
... AD6641 SPI TIMING REQUIREMENTS Table 5. Parameter Description t Setup time between the data and the rising edge of SCLK DS t Hold time between the data and the rising edge of SCLK DH t Period of the SCLK CLK t Setup time between CSB and SCLK S t Hold time between CSB and SCLK ...
Page 9
... DSDO SP_SCLK SP_SDO Figure 5. SP_SDO Propagation Delay SP_SCLK t SSF SP_SDFS Figure 6. Slave Mode SP_SDFS Setup/Hold Time CLK± t Sfill FILL± Figure 7. FILL± Setup and Hold Times Rev Page D11 D10 t HSF t Hfill AD6641 ...
Page 10
... AD6641 ABSOLUTE MAXIMUM RATINGS Table 6. Parameter Rating Electrical AVDD to AGND −0 +2.0 V DRVDD to DRGND −0 +2.0 V AGND to DRGND −0 +0.3 V AVDD to DRVDD −2 +2.0 V SPI_VDDIO to AVDD −2 +2.0 V SPI_VDDIO to DRVDD −2 +2.0 V PD[5:0]± to DRGND −0 DRVDD + 0.2 V PCLK± to DRGND −0 DRVDD + 0.2 V PDOR± ...
Page 11
... Serial Port Chip Select (Active Low). 1 3.3 V SPI I/O Supply. 1.9 V Analog Supply. Voltage Reference Input/Output. Nominally 0.75 V. Analog Input—True. Analog Input—Complement. Rev Page AVDD 41 AVDD 40 CML 39 AVDD 38 AVDD 37 AVDD 36 VIN– 35 VIN+ 34 AVDD 33 AVDD 32 AVDD 31 VREF 30 AVDD 29 SPI_VDDIO AD6641 ...
Page 12
... AD6641 Pin No. Mnemonic 40 CML 44 CLK+ 45 CLK− 49 FILL+ 50 FILL− 51 FULL 52 EMPTY 53 DUMP 55 PCLK− 56 PCLK+ Description Common-Mode Output. Enabled through the SPI, this pin provides a reference for the optimized internal bias voltage for VIN+ and VIN−. Clock Input—True. ...
Page 13
... Common-Mode Output. Enabled through the SPI, this pin provides a reference for the optimized internal bias voltage for VIN+ and VIN−. Clock Input—True. Rev Page AVDD 41 AVDD CML 40 39 AVDD 38 AVDD 37 AVDD 36 VIN– 35 VIN+ 34 AVDD 33 AVDD 32 AVDD 31 VREF 30 AVDD 29 SPI_VDDIO AD6641 ...
Page 14
... AD6641 Pin No. Mnemonic 45 CLK− 49 FILL+ 50 FILL− 51 FULL 52 EMPTY 53 DUMP 55 PCLK− 56 PCLK+ Description Clock Input—Complement. FIFO Fill Input (LVDS)—True. FIFO Fill Input (LVDS)—Complement. FIFO Full Output Indicator. FIFO Empty Output Indicator. FIFO Readback Input. Data Clock Output—Complement. ...
Page 15
... SNR (dBFS), –40° SNR (dBFS), +85° 100 Figure 15. Single-Tone SNR/SFDR vs. Input Frequency (f Rev Page AD6641 = −1 dBFS, unless otherwise noted. IN 491.52MSPS 368.0MHz @ –1.0dBFS SNR: 63.8dB ENOB: 10.5 BITS SFDR: 77dBc 60 80 100 120 140 160 180 200 220 240 FREQUENCY (MHz) 491 ...
Page 16
... AD6641 95 90 SFDR (dBc) 85 SFDR @ 30.3MHz, 1.8V 80 SFDR @ 30.3MHz, 1.9V SFDR @ 100.3MHz, 1.8V 75 SFDR @ 100.3MHz, 1.9V 70 SNR (dBFS) 65 SNRFS @ 30.3MHz, 1.8V SNRFS @ 30.3MHz, 1.9V 60 SNRFS @ 100.3MHz, 1.8V SNRFS @ 100.3MHz, 1. 250 300 350 400 SAMPLE RATE (MSPS) Figure 16. SNR/SFDR vs. Sample Rate and Supply 100 90 SFDR (dBFS) 80 SNR (dBFS) ...
Page 17
... Figure 25. Current and Power vs. Sample Rate Rev Page AD6641 SFDR (dBc) SNR (dBFS) 1.80 1.85 1.90 1.95 POWER SUPPLY (V) Figure 24. SNR/SFDR vs. Power Supply TOTAL POWER I AVDD I DRVDD 350 400 450 500 550 SAMPLE RATE (MSPS) 2 ...
Page 18
... AD6641 EQUIVALENT CIRCUITS AVDD CML AVDD VIN+ 500Ω AVDD SPI CONTROLLED 500Ω VIN– Figure 26. DC Equivalent Analog Input Circuit VIN+ 1.3pF VIN– Figure 27. AC Equivalent Analog Input Circuit AVDD AVDD 0.9V CLK+ 15kΩ 15kΩ OR FILL+ Figure 28. Equivalent CLK± and FILL± Input Circuit ...
Page 19
... DRVDD 350Ω 30kΩ SP_SDFS/ SP_SCLK MASTER/SLAVE Figure 34. Equivalent SP_SDFS and SP_SCLK Circuit VREF CTRL Rev Page AD6641 AVDD 20kΩ (00) (01) (10) (11) NOT USED SPI CTRL VREF SELECT 00: INTERNAL VREF 01: IMORT VREF 10: EXPORT VREF 11: NOT USED Figure 35. Equivalent VREF Circuit ...
Page 20
... AD6641 SPI REGISTER MAP Table 10. Memory Map Register Addr. Bit 7 (Hex) Parameter Name (MSB) Chip Configuration Registers 0x00 CHIP_PORT_CONFIG 0 0x01 CHIP_ID 0x02 CHIP_GRADE 0 Transfer Register 0xFF DEVICE_UPDATE ADC Functions 0x08 Modes 0 0x0D TEST_IO (For user-defined mode only, set Bits[3:0] = 1000 Pattern 1 only ...
Page 21
... Reserved Standby 0 after fill Fill reset Dump Fill 0 0x7F AD6641 Default Notes/ Comments Shown as fractional value of sampling clock period that is subtracted or added to initial t , SKEW see Figure 3). User Defined Pattern 1 LSB. User Defined Pattern 1 MSB. ...
Page 22
... AD6641 Addr. Bit 7 (Hex) Parameter Name (MSB) 0x105 Settle Count0 0x106 Settle Count1 0x107 Dump control 0x10A FIFO status 0x10B FIFO Dump Data0 0x10C FIFO Dump Data1 0x10F Read Offset Data0 0x110 Read Offset Data1 [7:6] = reserved 0x111 PPORT control [7:5] = reserved 0x112 ...
Page 23
... FIFO is determined by the following equation: Number of Samples = (FILL_CNT + 1) × 64 After the FIFO has begun filling at Event 2, the AD6641 asserts a full flag to indicate that the FIFO has finished capturing data and enters a wait state in which the device waits to receive the dump instruction from the DUMP pin or the SPI ...
Page 24
... AD6641 SPORT Master Mode (Single Capture) Details of the transaction diagram for serial master mode are shown in Figure 39 for single capture mode with the SDO output. Clock cycles are approximate because the fill and dump signals can be driven asynchronously. In this example, SCLK is derived from the master clock with a divide by 8 programmed from the SPI ...
Page 25
... FIFO and the FILL± pins pulsing high is used to stop the operation. This allows the history of the samples that preceded an event to be captured Figure 40. Parallel Mode Transaction Diagram Rev Page the sampling clock. Data begins 7 D16 D8 AD6641 8 ...
Page 26
... AD6641 begins shifting out the data stream. CMOS Output Interface The data stored in the FIFO can also be accessed via a 12-bit parallel CMOS interface. The maximum output throughput supported by the AD6641 is in the 12-bit CMOS mode and is th internally limited to 1/8 of the maximum input sample rate. ...
Page 27
... ADC core. This internal voltage reference can be adjusted by means of an SPI control. VREF The AD6641 VREF pin (Pin 31) allows the user to monitor the on-board voltage reference or provide an external reference (requires configuration through the SPI). The three optional settings are internal V (pin is connected to 20 kΩ ...
Page 28
... PLANE ORDERING GUIDE 1 Model Temperature Range AD6641BCPZ-500 −40°C to +85°C AD6641BCPZRL7-500 −40°C to +85°C AD6641-500EBZ RoHS Compliant Part. ©2011 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. 8.00 0.60 MAX 43 42 TOP 7 ...