74HC161D,652 NXP Semiconductors, 74HC161D,652 Datasheet - Page 2

• Manufacturer Part Number: 74HC161D,652
• Description: IC COUNTER BIN 4BIT SYNC 16-SOIC
• Manufacturer: NXP Semiconductors
• Series: 74HCr

Specifications of 74HC161D,652

• Package / Case: 16-SOIC (3.9mm Width)
• Logic Type: Binary Counter
• Direction: Up
• Number Of Elements: 1
• Number Of Bits Per Element: 4
• Reset: Asynchronous
• Timing: Asynchronous/Synchronous
• Count Rate: 48MHz
• Trigger Type: Positive Edge
• Voltage - Supply: 2 V ~ 6 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Counter Type: Binary Counters
• Logic Family: 74HC
• Number Of Bits: 4
• Counting Method: Synchronous
• Operating Supply Voltage: 2 V to 6 V
• Operating Temperature Range: - 40 C to + 125 C
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 568-4848-5; 74HC161D; 74HC161D,652; 74HC161D; 933714520652

Philips Semiconductors
FEATURES
GENERAL DESCRIPTION
The 74HC/HCT161 are high-speed Si-gate CMOS devices
and are pin compatible with low power Schottky TTL
(LSTTL). They are specified in compliance with JEDEC
standard no. 7A.
The 74HC/HCT161 are synchronous presettable binary
counters which feature an internal look-ahead carry and
can be used for high-speed counting.
Synchronous operation is provided by having all flip-flops
clocked simultaneously on the positive-going edge of the
clock (CP).
The outputs (Q
HIGH or LOW level. A LOW level at the parallel enable
QUICK REFERENCE DATA
GND = 0 V; T
December 1990
SYMBOL PARAMETER
t
f
C
C
PHL
max
Synchronous counting and loading
Two count enable inputs for n-bit cascading
Positive-edge triggered clock
Asynchronous reset
Output capability: standard
I
Presettable synchronous 4-bit binary
counter; asynchronous reset
I
PD
CC
/ t
category: MSI
PLH
propagation delay
maximum clock frequency
input capacitance
power dissipation
capacitance per package
amb
CP to Q
CP to TC
MR to Q
MR to TC
CET to TC
0
to Q
= 25 C; t
3
) of the counters may be preset to a
n
n
r
= t
f
= 6 ns
CONDITIONS
C
V
notes 1 and 2
CC
L
= 15 pF;
= 5 V
19
21
20
20
10
44
3.5
33
HC
TYPICAL
2
input (PE) disables the counting action and causes the
data at the data inputs (D
counter on the positive-going edge of the clock (providing
that the set-up and hold time requirements for PE are met).
Preset takes place regardless of the levels at count enable
inputs (CEP and CET).
A LOW level at the master reset input (MR) sets all four
outputs of the flip-flops (Q
of the levels at CP, PE, CET and CEP inputs (thus
providing an asynchronous clear function).
The look-ahead carry simplifies serial cascading of the
counters. Both count enable inputs (CEP and CET) must
be HIGH to count. The CET input is fed forward to enable
the terminal count output (TC). The TC output thus
enabled will produce a HIGH output pulse of a duration
approximately equal to a HIGH level output of Q
pulse can be used to enable the next cascaded stage.
The maximum clock frequency for the cascaded counters
is determined by the CP to TC propagation delay and CEP
to CP set-up time, according to the following formula:
f
max
20
24
25
26
14
45
3.5
35
HCT
=
-------------------------------------------------------------------------------------------------- -
t
P(max)
ns
ns
ns
ns
ns
MHz
pF
pF
UNIT
(CP to TC)
Notes
1. C
2. For HC the condition is
dynamic power dissipation
(P
f
f
outputs
C
pF
V
For HCT the condition is
i
o
0
0
CC
PD
= input frequency in MHz
L
1
= output frequency in MHz
(C
D
to Q
V
V
to D
+
= output load capacitance in
P
where:
I
I
in W):
L
t
is used to determine the
= supply voltage in V
D
= GND to V
= GND to V
SU
3
= C
3
(C
) to be loaded into the
) to LOW level regardless
V
74HC/HCT161
(CEP to CP)
CC
L
Product specification
PD
2
V
CC
V
f
o
CC
) = sum of
CC
CC
2
2
f
o
1.5 V
)
f
i
0
. This