74HC4017DB,118 NXP Semiconductors, 74HC4017DB,118 Datasheet

IC JOHNSON DECADE COUNTER 16SSOP

74HC4017DB,118

Manufacturer Part Number
74HC4017DB,118
Description
IC JOHNSON DECADE COUNTER 16SSOP
Manufacturer
NXP Semiconductors
Series
74HCr
Datasheet

Specifications of 74HC4017DB,118

Package / Case
16-SSOP
Logic Type
Counter, Decade
Direction
Up
Number Of Elements
1
Number Of Bits Per Element
10
Reset
Asynchronous
Count Rate
83MHz
Trigger Type
Positive Edge
Voltage - Supply
2 V ~ 6 V
Operating Temperature
-40°C ~ 125°C
Mounting Type
Surface Mount
Counter Type
Decade Counters
Logic Family
74HC
Number Of Bits
10
Operating Supply Voltage
2 V to 6 V
Operating Temperature Range
- 40 C to + 125 C
Mounting Style
SMD/SMT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Timing
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
74HC4017DB-T
74HC4017DB-T
935189360118
1. General description
2. Features
The 74HC4017; 74HCT4017 is a high-speed Si-gate CMOS device and is pin compatible
with the HEF4017.
The 74HC4017; 74HCT4017 is a 5-stage Johnson decade counter with 10 decoded active
HIGH outputs (Q0 to Q9), an active LOW output from the most significant flip-flop (Q5-9),
active HIGH and active LOW clock inputs (CP0 and CP1) and an overriding asynchronous
master reset input (MR).
The counter is advanced by either a LOW-to-HIGH transition at CP0 while CP1 is LOW or
a HIGH-to-LOW transition at CP1 while CP0 is HIGH (see
When cascading counters, the Q5-9 output, which is LOW while the counter is in states 5,
6, 7, 8 and 9, can be used to drive the CP0 input of the next counter.
A HIGH on MR resets the counter to zero (Q0 = Q5-9 = HIGH; Q1 to Q9 = LOW)
independent of the clock inputs (CP0 and CP1).
Automatic code correction of the counter is provided by an internal circuit: following any
illegal code the counter returns to a proper counting mode within 11 clock pulses.
74HC4017; 74HCT4017
Johnson decade counter with 10 decoded outputs
Rev. 03 — 8 January 2008
Multiple package options
Complies with JEDEC standard no. 7 A
ESD protection:
Specified from 40 C to +85 C and from 40 C to +125 C
HBM JESD22-A114E exceeds 2000 V
MM JESD22-A115-A exceeds 200 V
Table
3).
Product data sheet

Related parts for 74HC4017DB,118

74HC4017DB,118 Summary of contents

Page 1

Johnson decade counter with 10 decoded outputs Rev. 03 — 8 January 2008 1. General description The 74HC4017; 74HCT4017 is a high-speed Si-gate CMOS device and is pin compatible with the HEF4017. The 74HC4017; 74HCT4017 is a 5-stage ...

Page 2

... NXP Semiconductors 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name 74HC4017 74HC4017N +125 C 74HC4017D +125 C 74HC4017DB +125 C 74HC4017PW +125 C 74HC4017BQ +125 C 74HCT4017 74HCT4017N +125 C 74HCT4017D +125 C 74HCT4017BQ +125 C 4. Functional diagram CP1 13 CP0 Fig 1. Functional diagram 74HC_HCT4017_3 Product data sheet 74HC4017 ...

Page 3

... NXP Semiconductors CP1 13 CP0 Fig 2. Logic symbol CP1 CP0 Fig 4. Logic diagram 74HC_HCT4017_3 Product data sheet Johnson decade counter with 10 decoded outputs Q5-9 12 001aah239 Fig 3. IEC logic symbol Rev. 03 — 8 January 2008 74HC4017; 74HCT4017 CTRDIV10/DEC 14 0 & 001aah240 001aah243 © NXP B.V. 2008. All rights reserved. ...

Page 4

... NXP Semiconductors CP0 INPUT CP1 INPUT MR INPUT Q0 OUTPUT Q1 OUTPUT Q2 OUTPUT Q3 OUTPUT Q4 OUTPUT Q5 OUTPUT Q6 OUTPUT Q7 OUTPUT Q8 OUTPUT Q9 OUTPUT Q5-9 OUTPUT Fig 5. Timing diagram 74HC_HCT4017_3 Product data sheet 74HC4017; 74HCT4017 Johnson decade counter with 10 decoded outputs Rev. 03 — 8 January 2008 001aah244 © NXP B.V. 2008. All rights reserved. ...

Page 5

... NXP Semiconductors 5. Pinning information 5.1 Pinning 74HC4017 74HCT4017 GND 8 Fig 6. Pin configuration DIP16, SO16 and (T)SSOP16 5.2 Pin description Table 2. Pin description Symbol Pin Q[0: 10 decoded output GND 8 Q5-9 12 CP1 13 CP0 74HC_HCT4017_3 Product data sheet Johnson decade counter with 10 decoded outputs ...

Page 6

... NXP Semiconductors 6. Functional description [1] Table 3. Function table MR CP0 [ HIGH voltage level LOW voltage level don’t care; = LOW-to-HIGH transition; = HIGH-to-LOW transition; 7. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). ...

Page 7

... NXP Semiconductors 8. Recommended operating conditions Table 5. Recommended operating conditions Symbol Parameter 74HC4017 V supply voltage CC V input voltage I V output voltage input transition rise and fall rate V T ambient temperature amb 74HCT4017 V supply voltage CC V input voltage I V output voltage input transition rise and fall rate V ...

Page 8

... NXP Semiconductors Table 6. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions V LOW-level output voltage 4.0 mA 5.2 mA input leakage current supply current 6 input I capacitance 74HCT4017 V HIGH-level input voltage V LOW-level input voltage V HIGH-level output voltage ...

Page 9

... NXP Semiconductors 10. Dynamic characteristics Table 7. Dynamic characteristics GND = ns pF; see Symbol Parameter Conditions 74HC4017 t propagation CP0 to Qn; CP0 to Q5-9; pd delay see Figure CP1 to Qn; CP1 to Q5-9; see Figure HIGH to LOW MR to Q[1:9]; PHL propagation see Figure 10 delay LOW to HIGH MR to Q5-9, Q0; ...

Page 10

... NXP Semiconductors Table 7. Dynamic characteristics GND = ns pF; see Symbol Parameter Conditions t set-up time CP1 to CP0; CP0 to CP1; su see Figure hold time CP1 to CP0; CP0 to CP1; h see Figure recovery time MR to CP0 and rec MR to CP1; see maximum CP0 or CP1; see max ...

Page 11

... NXP Semiconductors Table 7. Dynamic characteristics GND = ns pF; see Symbol Parameter Conditions t transition time see Figure pulse width CP0 and CP1 (HIGH or W LOW); see (HIGH); see set-up time CP1 to CP0; CP0 to CP1; su see Figure hold time CP1 to CP0; CP0 to CP1; h see ...

Page 12

... NXP Semiconductors 11. Waveforms V I CP0 input GND V I CP1 input GND Measurement points are given in V and V are typical voltage output levels that occur with the output load Fig 8. Waveforms showing the set-up and hold times for CP0 to CP1 and CP1 to CP0 ...

Page 13

... NXP Semiconductors CP0 input CP1 input output Q0 output Measurement points are given in V and V are typical voltage output levels that occur with the output load Conditions: CP1 = LOW while CP0 is triggered on a LOW-to-HIGH transition and CP0 = HIGH, while CP1 is triggered on a HIGH-to-LOW transition. ...

Page 14

... NXP Semiconductors PULSE GENERATOR Test data is given in Table 9. Definitions test circuit Termination resistance should be equal to output impedance Load capacitance including jig and probe capacitance Load resistance Test selection switch. Fig 11. Load circuitry for measuring switching times Table 9. Test data Type ...

Page 15

... NXP Semiconductors clock Fig 12. Counter expansion Remark essential not to enable the counter on CP1 when CP0 is HIGH CP0 when CP1 is LOW, as this would cause an extra count. Figure 13 74HC4017; 74HCT4017. Since the 74HC4017; 74HCT4017 has an asynchronous reset, the output pulse widths are narrow (minimum expected pulse width is 6 ns). The output pulse widths can be enlarged by inserting an RC network at the MR input ...

Page 16

... NXP Semiconductors 13. Package outline DIP16: plastic dual in-line package; 16 leads (300 mil pin 1 index 1 DIMENSIONS (inch dimensions are derived from the original mm dimensions UNIT max. min. max. mm 4.2 0.51 3.2 inches 0.17 0.02 0.13 Note 1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included. ...

Page 17

... NXP Semiconductors SO16: plastic small outline package; 16 leads; body width 3 pin 1 index 1 DIMENSIONS (inch dimensions are derived from the original mm dimensions) A UNIT max. 0.25 1.45 mm 1.75 0.25 0.10 1.25 0.010 0.057 inches 0.069 0.01 0.004 0.049 Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. ...

Page 18

... NXP Semiconductors SSOP16: plastic shrink small outline package; 16 leads; body width 5 pin 1 index 1 e DIMENSIONS (mm are the original dimensions) A UNIT max. 0.21 1. 0.25 0.05 1.65 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION IEC SOT338-1 Fig 16. Package outline SOT338-1 (SSOP16) ...

Page 19

... NXP Semiconductors TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4 pin 1 index 1 DIMENSIONS (mm are the original dimensions) A UNIT max. 0.15 0.95 mm 1.1 0.25 0.05 0.80 Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. ...

Page 20

... NXP Semiconductors DHVQFN16: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 16 terminals; body 2.5 x 3.5 x 0.85 mm terminal 1 index area terminal 1 index area DIMENSIONS (mm are the original dimensions) (1) A UNIT max. 0.05 0. 0.2 0.00 0.18 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. ...

Page 21

... Johnson decade counter with 10 decoded outputs Data sheet status Product data sheet • The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. • Legal texts have been adapted to the new company name where appropriate. • Section 3: DHVQFN16 package added. • ...

Page 22

... Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice ...

Page 23

... NXP Semiconductors 18. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 4 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 5 Pinning information . . . . . . . . . . . . . . . . . . . . . . 5 5.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 5.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5 6 Functional description . . . . . . . . . . . . . . . . . . . 6 7 Limiting values Recommended operating conditions Static characteristics Dynamic characteristics . . . . . . . . . . . . . . . . . . 9 11 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 12 Application information Package outline . . . . . . . . . . . . . . . . . . . . . . . . 16 14 Abbreviations ...

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