74HC163D,652 NXP Semiconductors, 74HC163D,652 Datasheet - Page 2

• Manufacturer Part Number: 74HC163D,652
• Description: IC SYNC 4BIT BINAR COUNT 16SOIC
• Manufacturer: NXP Semiconductors
• Series: 74HCr

Specifications of 74HC163D,652

• Package / Case: 16-SOIC (3.9mm Width)
• Logic Type: Binary Counter
• Direction: Up
• Number Of Elements: 1
• Number Of Bits Per Element: 4
• Reset: Synchronous
• Timing: Synchronous
• Count Rate: 55MHz
• Trigger Type: Positive Edge
• Voltage - Supply: 2 V ~ 6 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Counter Type: Binary Counters
• Logic Family: 74HC
• Number Of Bits: 4
• Counting Method: Synchronous
• Operating Supply Voltage: 2 V to 6 V
• Operating Temperature Range: - 40 C to + 125 C
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 74HC163D; 74HC163D; 933714540652

Philips Semiconductors
FEATURES
GENERAL DESCRIPTION
The 74HC/HCT163 are high-speed Si-gate CMOS devices
and are pin compatible with low power Schottky TTL
(LSTTL). They are specified in compliance with JEDEC
standard no. 7A.
The 74HC/HCT163 are synchronous presettable binary
counters which feature an internal look-ahead carry and
can be used for high-speed counting.
Synchronous operation is provided by having all flip-flops
clocked simultaneously on the positive-going edge of the
clock (CP).
The outputs (Q
HIGH or LOW level. A LOW level at the parallel enable
input (PE) disables the counting action and causes the
data at the data inputs (D
counter on the positive-going edge of the clock (providing
that the set-up and hold time requirements for PE are met).
QUICK REFERENCE DATA
GND = 0 V; T
December 1990
t
f
C
C
SYMBOL
PHL
max
Synchronous counting and loading
Two count enable inputs for n-bit cascading
Positive-edge triggered clock
Synchronous reset
Output capability: standard
I
Presettable synchronous 4-bit binary
counter; synchronous reset
I
PD
CC
/ t
category: MSI
PLH
propagation delay
maximum clock frequency
input capacitance
power dissipation
capacitance per package
amb
CP to Q
CP to TC
CET to TC
0
to Q
= 25 C; t
PARAMETER
3
) of the counters may be preset to a
n
0
to D
r
= t
f
3
= 6 ns
) to be loaded into the
CONDITIONS
C
V
notes 1 and 2 33
CC
L
= 15 pF;
= 5 V
17
21
11
51
3.5 3.5
HC
TYPICAL
2
Preset takes place regardless of the levels at count enable
inputs (CEP and CET).
For the “163” the clear function is synchronous.
A LOW level at the master reset input (MR) sets all four
outputs of the flip-flops (Q
next positive-going transition on the clock (CP) input
(provided that the set-up and hold time requirements for
MR are met). This action occurs regardless of the levels at
PE, CET and CEP inputs.
This synchronous reset feature enables the designer to
modify the maximum count with only one external NAND
gate.
The look-ahead carry simplifies serial cascading of the
counters. Both count enable inputs (CEP and CET) must
be HIGH to count. The CET input is fed forward to enable
the terminal count output (TC). The TC output thus
enabled will produce a HIGH output pulse of a duration
approximately equal to a HIGH level output of Q
pulse can be used to enable the next cascaded stage.
The maximum clock frequency for the cascaded counters
is determined by the CP to TC propagation delay and CEP
to CP set-up time, according to the following formula:
f
max
20
25
14
50
35
HCT
=
------------------------------------------------------------------------------------------------ -
t
P max
ns
ns
ns
MHz
pF
pF
UNIT
(CP to TC)
Notes
1. C
2. For HC the condition is
dynamic power dissipation
(P
where:
f
f
outputs
C
pF
V
For HCT the condition is
1
i
o
CC
0
+
PD
L
D
(C
P
= input frequency in MHz
= output frequency in MHz
to Q
= output load capacitance in
t
V
V
D
SU
in W):
is used to determine the
L
= supply voltage in V
I
I
= C
= GND to V
= GND to V
(CEP to CP)
3
V
) to LOW level after the
74HC/HCT163
PD
CC
(C
Product specification
2
L
V
f
CC
V
o
) = sum of
CC
CC
CC
2
2
f
i
1.5 V
f
0
o
. This
)