HEF4040BT,653 NXP Semiconductors, HEF4040BT,653 Datasheet
HEF4040BT,653
Specifications of HEF4040BT,653
HEF4040BTD-T
HEF4040BTD-T
Related parts for HEF4040BT,653
HEF4040BT,653 Summary of contents
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HEF4040B 12-stage binary ripple counter Rev. 06 — 25 November 2009 1. General description The HEF4040B is a 12-stage binary ripple counter with a clock input (CP), an overriding asynchronous master reset input (MR) and twelve fully buffered outputs (Q0 ...
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... NXP Semiconductors 5. Functional diagram CP MR Fig 1. Functional diagram Fig 2. Logic diagram CP input MR input Q10 Q11 Fig 3. Timing diagram HEF4040B_6 Product data sheet 10 T 12-STAGE COUNTER Rev. 06 — 25 November 2009 HEF4040B 12-stage binary ripple counter Q10 Q11 001aad589 Q11 001aae615 128 256 ...
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... NXP Semiconductors 6. Pinning information 6.1 Pinning Fig 4. Pin configuration 6.2 Pin description Table 2. Pin description Symbol Pin Q11 13, 12, 14, 15 HEF4040B_6 Product data sheet HEF4040B Q11 Q10 001aae614 Description ground supply voltage parallel output clock input (HIGH-to-LOW edge-triggered) master reset input (active HIGH) supply voltage Rev. 06 — ...
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... NXP Semiconductors 7. Limiting values Table 3. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter V supply voltage DD I input clamping current IK V input voltage I I output clamping current OK I input/output current I/O I supply current DD T storage temperature stg ...
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... NXP Semiconductors Table 5. Static characteristics …continued unless otherwise specified Symbol Parameter HIGH-level output voltage | LOW-level output voltage OL I HIGH-level output current LOW-level output current OL I input leakage current LI I supply current DD C input capacitance I 10. Dynamic characteristics Table 6. Dynamic characteristics ° ...
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... NXP Semiconductors Table 6. Dynamic characteristics ° unless otherwise specified; for test circuit see SS amb Symbol Parameter Conditions t transition time see t t pulse width CP input HIGH; W minimum width; see MR input HIGH; minimum width; see t recovery time MR input; rec see f maximum CP input; max ...
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... NXP Semiconductors 11. Waveforms MR input CP input output output Logic levels: V and V are typical output voltage levels that occur with the output load Transition times: transition time (t Measurement points are given in Fig 5. Waveforms showing propagation delays for and CP to Q0, minimum MR and CP pulse widths Table 8 ...
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... NXP Semiconductors negative positive a. Input waveforms b. Test circuit Test data is given in Table 9. Definitions test circuit: DUT = Device Under Test load capacitance, including the jig and probe capacitance load resistance, which should be equal to the output impedance of the pulse generator. L Fig 6. Test circuit for measuring switching times Table 9 ...
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... NXP Semiconductors 12. Package outline DIP16: plastic dual in-line package; 16 leads (300 mil pin 1 index 1 DIMENSIONS (inch dimensions are derived from the original mm dimensions UNIT b max. min. max. 1.73 mm 4.2 0.51 3.2 1.30 0.068 inches 0.17 0.02 0.13 0.051 Note 1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included. ...
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... NXP Semiconductors SO16: plastic small outline package; 16 leads; body width 3 pin 1 index 1 e DIMENSIONS (inch dimensions are derived from the original mm dimensions) A UNIT max. 0.25 1.45 mm 1.75 0.25 0.10 1.25 0.010 0.057 inches 0.069 0.01 0.004 0.049 Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. ...
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... NXP Semiconductors 13. Revision history Table 10. Revision history Document ID Release date HEF4040B_6 20091125 • Modifications: Section 2 HEF4040B_5 20090709 HEF4040B_4 20090304 HEF4040B_CNV_3 19950101 HEF4040B_CNV_2 19950101 HEF4040B_6 Product data sheet Data sheet status Change notice Product data sheet - “Features”, Δt/ΔV values updated. ...
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... Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice ...
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... NXP Semiconductors 16. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 4 Ordering information . . . . . . . . . . . . . . . . . . . . . 1 5 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 6 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 7 Limiting values Recommended operating conditions Static characteristics Dynamic characteristics . . . . . . . . . . . . . . . . . . 5 11 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 12 Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 9 13 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 11 14 Legal information ...