74HC390PW,112 NXP Semiconductors, 74HC390PW,112 Datasheet - Page 2

• Manufacturer Part Number: 74HC390PW,112
• Description: IC DUAL DEC RIPPLE COUNT 16TSSOP
• Manufacturer: NXP Semiconductors
• Series: 74HCr
• Type: Decader

Specifications of 74HC390PW,112

• Package / Case: 16-TSSOP
• Logic Type: Counter, Decade
• Direction: Up
• Number Of Elements: 2
• Number Of Bits Per Element: 4
• Reset: Asynchronous
• Count Rate: 71MHz
• Trigger Type: Negative Edge
• Voltage - Supply: 2 V ~ 6 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Mounting Style: SMD/SMT
• Technology: CMOS
• Number Of Elements: 2
• Number Of Bits: 4
• Logic Family: HC
• Logical Function: Counter/Divider
• Operating Supply Voltage (typ): 5V
• Output Type: Standard
• Package Type: TSSOP
• Propagation Delay Time: 315ns
• Operating Temp Range: -40C to 125C
• Operating Supply Voltage (min): 2V
• Operating Supply Voltage (max): 6V
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 16
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Timing: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 74HC390PW; 74HC390PW; 935189060112

Philips Semiconductors
FEATURES
GENERAL DESCRIPTION
The 74HC/HCT390 are high-speed Si-gate CMOS devices
and are pin compatible with low power Schottky TTL
(LSTTL). They are specified in compliance with JEDEC
standard no. 7A.
The 74HC/HCT390 are dual 4-bit decade ripple counters
divided into four separately clocked sections. The counters
have two divide-by-2 sections and two divide-by-5
sections. These sections are normally used in a BCD
QUICK REFERENCE DATA
GND = 0 V; T
Notes
1. C
2. For HC the condition is V
December 1990
t
f
C
C
SYMBOL
PHL
max
Two BCD decade or bi-quinary counters
One package can be configured to divide-by-2, 4, 5, 10,
20, 25, 50 or 100
Two master reset inputs to clear each decade counter
individually
Output capability: standard
I
Dual decade ripple counter
I
PD
CC
f
f
C
V
For HCT the condition is V
i
o
/ t
CC
PD
L
category: MSI
= output frequency in MHz
= input frequency in MHz
(C
PLH
= output load capacitance in pF
P
is used to determine the dynamic power dissipation (P
= supply voltage in V
L
D
= C
V
propagation delay
maximum clock frequency nCP
input capacitance
power dissipation capacitance per counter
amb
CC
PD
nCP
nCP
nCP
nCP
nMR to Q
2
= 25 C; t
V
f
0
1
1
1
o
CC
to nQ
to nQ
to nQ
to nQ
) = sum of outputs
2
n
f
r
0
1
2
3
i
= t
I
PARAMETER
I
f
= GND to V
= GND to V
= 6 ns
(C
L
V
CC
2
CC
CC
0
, nCP
f
o
1.5 V
) where:
1
2
decade or bi-quinary configuration, since they share a
common master reset input (nMR). If the two master reset
inputs (1MR and 2MR) are used to simultaneously clear all
8 bits of the counter, a number of counting configurations
are possible within one package. The separate clocks
(nCP
frequency division applications of divide-by-2, 4, 5, 10, 20,
25, 50 or 100.
Each section is triggered by the HIGH-to-LOW transition of
the clock inputs (nCP
operation, the nQ
of, the divide-by-5 section. For bi-quinary decade
operation, the nQ
and nQ
The master reset inputs (1MR and 2MR) are active HIGH
asynchronous inputs to each decade counter which
operates on the portion of the counter identified by the “1”
and “2” prefixes in the pin configuration. A HIGH level on
the nMR input overrides the clocks and sets the four
outputs LOW.
D
C
notes 1 and 2
in W):
L
0
= 15 pF; V
and nCP
0
becomes the decade output.
CONDITIONS
1
CC
) of each section allow ripple counter or
0
3
output is connected to the nCP
output is connected to the nCP
= 5 V
0
and nCP
1
14
15
23
15
16
66
3.5
20
74HC/HCT390
). For BCD decade
HC
TYPICAL
Product specification
18
19
26
19
18
61
3.5
21
HCT
ns
ns
ns
ns
ns
MHz
pF
pF
UNIT
1
0
input
input