IC DUAL DEC RIPPLE COUNT 16SOIC

74HC390D,653

Manufacturer Part Number74HC390D,653
DescriptionIC DUAL DEC RIPPLE COUNT 16SOIC
ManufacturerNXP Semiconductors
Series74HC
TypeDecade
74HC390D,653 datasheet
 


Specifications of 74HC390D,653

Package / Case16-SOIC (3.9mm Width)Logic TypeCounter, Decade
DirectionUpNumber Of Elements2
Number Of Bits Per Element4ResetAsynchronous
Count Rate71MHzTrigger TypeNegative Edge
Voltage - Supply2 V ~ 6 VOperating Temperature-40°C ~ 125°C
Mounting TypeSurface MountCounter TypeDecade Counters
Logic Family74HCNumber Of Bits4
Operating Supply Voltage2 V to 6 VOperating Temperature Range- 40 C to + 125 C
Mounting StyleSMD/SMTTechnologyCMOS
Number Of Elements2Logical FunctionCounter/Divider
Operating Supply Voltage (typ)5VOutput TypeStandard
Package TypeSOPropagation Delay Time315ns
Operating Temp Range-40C to 125COperating Supply Voltage (min)2V
Operating Supply Voltage (max)6VOperating Temperature ClassificationAutomotive
MountingSurface MountPin Count16
Lead Free Status / RoHS StatusLead free / RoHS CompliantTiming-
Other names74HC390D-T
74HC390D-T
933714720653
  
1
Page 1
2
Page 2
3
Page 3
4
Page 4
5
Page 5
6
Page 6
7
Page 7
Page 2/7

Download datasheet (47Kb)Embed
PrevNext
Philips Semiconductors
Dual decade ripple counter
FEATURES
Two BCD decade or bi-quinary counters
One package can be configured to divide-by-2, 4, 5, 10,
20, 25, 50 or 100
Two master reset inputs to clear each decade counter
individually
Output capability: standard
I
category: MSI
CC
GENERAL DESCRIPTION
The 74HC/HCT390 are high-speed Si-gate CMOS devices
and are pin compatible with low power Schottky TTL
(LSTTL). They are specified in compliance with JEDEC
standard no. 7A.
The 74HC/HCT390 are dual 4-bit decade ripple counters
divided into four separately clocked sections. The counters
have two divide-by-2 sections and two divide-by-5
sections. These sections are normally used in a BCD
QUICK REFERENCE DATA
GND = 0 V; T
= 25 C; t
= t
= 6 ns
amb
r
f
SYMBOL
PARAMETER
t
/ t
propagation delay
PHL
PLH
nCP
to nQ
0
0
nCP
to nQ
1
1
nCP
to nQ
1
2
nCP
to nQ
1
3
nMR to Q
n
f
maximum clock frequency nCP
max
C
input capacitance
I
C
power dissipation capacitance per counter
PD
Notes
1. C
is used to determine the dynamic power dissipation (P
PD
2
P
= C
V
f
(C
D
PD
CC
i
f
= input frequency in MHz
i
f
= output frequency in MHz
o
2
(C
V
f
) = sum of outputs
L
CC
o
C
= output load capacitance in pF
L
V
= supply voltage in V
CC
2. For HC the condition is V
= GND to V
I
For HCT the condition is V
= GND to V
I
December 1990
decade or bi-quinary configuration, since they share a
common master reset input (nMR). If the two master reset
inputs (1MR and 2MR) are used to simultaneously clear all
8 bits of the counter, a number of counting configurations
are possible within one package. The separate clocks
(nCP
and nCP
0
frequency division applications of divide-by-2, 4, 5, 10, 20,
25, 50 or 100.
Each section is triggered by the HIGH-to-LOW transition of
the clock inputs (nCP
operation, the nQ
of, the divide-by-5 section. For bi-quinary decade
operation, the nQ
and nQ
0
The master reset inputs (1MR and 2MR) are active HIGH
asynchronous inputs to each decade counter which
operates on the portion of the counter identified by the “1”
and “2” prefixes in the pin configuration. A HIGH level on
the nMR input overrides the clocks and sets the four
outputs LOW.
C
= 15 pF; V
L
, nCP
0
1
notes 1 and 2
in W):
D
2
V
f
) where:
L
CC
o
CC
1.5 V
CC
2
Product specification
74HC/HCT390
) of each section allow ripple counter or
1
and nCP
). For BCD decade
0
1
output is connected to the nCP
0
output is connected to the nCP
3
becomes the decade output.
TYPICAL
CONDITIONS
HC
HCT
= 5 V
CC
14
18
15
19
23
26
15
19
16
18
66
61
3.5
3.5
20
21
input
1
input
0
UNIT
ns
ns
ns
ns
ns
MHz
pF
pF