SL1935D ETC, SL1935D Datasheet

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SL1935D

Manufacturer Part Number
SL1935D
Description
Single Chip Synthesized Zero IF Tuner
Manufacturer
ETC
Datasheet

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
SL1935D
Manufacturer:
ZARLINK
Quantity:
20 000
Part Number:
SL1935D/KG/NP1Q
Manufacturer:
ZARLINK
Quantity:
20 000
Features
Applications
Satellite receiver systems.
Data communications systems.
Single chip synthesised tuner solution for quadrature
down conversion, L-band to Zero IF.
DVB compliant, operating dynamic range -70 to
-20dBm.
Compatible with DSS and DVB variable symbol rate
applications.
Selectable baseband path, programmable through
I
Excellent quadrature balance up to 30MHz
baseband
Excellent immunity to spurious second harmonic
(RF and LO) mixing effects.
Low oscillator phase noise and reradiation.
High output referred linearity for low distortion and
multi channel application.
Integral fast mode compliant I
frequency synthesiser, designed for high comparison
frequencies and low phase noise performance.
Buffered crystal output for clocking QPSK
demodulator.
ESD protection (Normal ESD handling procedures
should be observed).
2
C bus.
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.
Copyright 2003 - 2004, Zarlink Semiconductor Inc. All Rights Reserved.
XTALCAP
BUFREF
2
C bus controlled PLL
VCCD
XTAL
IOUT
OFIA
OFIB
VCC
VCC
VCC
ADD
SDA
RFB
VEE
SCL
IFIA
IFIB
RF
Figure 1. Pin connections
18
1
Zarlink Semiconductor Inc.
1
Single Chip Synthesized Zero IF Tuner
Description
The SL1935 is a complete single chip
Zero IF tuner and operates from 950 to 2150MHz. It
includes an on-board low phase noise PLL frequency
synthesiser and low noise LNA/AGC. The SL1935 is
intended primarily for application in digital satellite Network
Interface Modules and performs the complete tuner
function.
The device contains all elements necessary, with the
exception of local oscillator tuning network and crystal
reference, to produce a high performance I(n-phase) &
Q(uadrature) downconversion tuner function. Due to the
high signal handling design the device does not require
any front end tracking filters.
The SL1935 includes selectable baseband signal paths,
allowing application with two externally definable filter
bandwidths, facilitating application in variable symbol
rate and simulcast systems. The SL1935 is optimised to
interface with the VP310 (ADC/QPSK/FEC) Satellite
Channel Decoder, available from Zarlink Semiconductor
and offers a full front end solution.
SL1935D/KG/NP1Q (Tape and Reel) 36 pin SSOP
36
19
SL1935D/KG/NP1P (Tubes) 36 pin SSOP
PUMP
DRIVE
PORT P0
VEE
TANKS
TANKSB
VEE
TANKV
TANKVB
VEE
IFQA
IFQB
VCC
OFQA
OFQB
VEE
QOUT
AGCCONT
Ordering Information
I
2
C
bus controlled
SL1935
April 2004

Related parts for SL1935D

SL1935D Summary of contents

Page 1

... Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc. Copyright 2003 - 2004, Zarlink Semiconductor Inc. All Rights Reserved. Single Chip Synthesized Zero IF Tuner SL1935D/KG/NP1Q (Tape and Reel) 36 pin SSOP Description The SL1935 is a complete single chip Zero IF tuner and operates from 950 to 2150MHz. It includes an on-board low phase noise PLL frequency synthesiser and low noise LNA/AGC ...

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SL1935 RF Section VCC RF section 7,10,13,24 VCCD PLL section 6 VEE 16,21,27,30,33 TANKV 29 TANKVB 28 VCOV TANKS 32 TANKSB 31 VCOS PLL Section SDA 3 SCL 4 ADD 18 REF OSC XTAL 2 XTALCAP RFB ...

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Table 1. Quick Reference Data Characteristic Operating range Input dynamic range VSWR with input match Input NF @ -70dBm operating sensitivity @ -60dBm operating sensitivity IPIP3 @ -20dBm operating sensitivity IPIP2@ -20dBm operating sensitivity IPP1dB@ -20dBm operating sensitivity Baseband output ...

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SL1935 Quadrature Downconverter Section - continued The oscillators share a common varactor line drive and both require an external varactor tuned resonator optimised for low phase noise performance. The recommended application circuit for the local oscillators is detailed in Fig.9 ...

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The STOP condition can be generated after any data byte, if however it occurs during a byte transmission, the previous byte data is retained. To facilitate smooth fine tuning, the frequency data bytes are only accepted by the device after ...

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SL1935 Table 4. Test modes Note: * Clocks need to be present on ...

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Table 9a. Write data format (MSB is transmitted first) MSB Address Programmable 0 2 divider 7 6 Programmable 2 2 divider Control data 1 C1 Control data T2 T1 Table 9b. Read data format (MSB is transmitted ...

Page 8

SL1935 70dB minimum, AGC < 0.75V 0.5 1 120 110 100 Figure 5. Variation in IIP3 with system gain (typical) 170 160 ...

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Converter gain seting (dB) from RF inputs OFIA/OFQA or OFIB/OFQB outputs Figure 7. Variation in P1dB with converter gain (typical ...

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SL1935 900 1000 1100 1200 -70 -72 vcos enabled -74 -76 -78 -80 -82 -84 -86 Conditions: Loop filter as per standard application shown in Figure 21 Charge pump = 130uA -88 Fcomp = 65.5kHz or 125kHz -90 Figure 10. ...

Page 11

OFIA/OFIB OFQA/OFQB Figure 13. Example baseband interstage filter for 30MS/s 220nF 100 Ω Figure 14. Nominal baseband output load test condition 82pF Figure 15. Crystal oscillator application (typical) 100nF 1k Ω 1k Ω 3.9pF 1k Ω 15pF 1 XTALCAP ...

Page 12

SL1935 RFIN Table 10. Electrical Characteristics Test conditions (unless otherwise stated); Tamb = - + Vee= 0V, Vcc =Vccd = 5V+-5%. These characteristics are guaranteed by either production test or design. They apply within the specified ...

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Table 10. Electrical Characteristics Characteristic System dynamic range System gain roll off System gain variation with temperature System I Q gain match System I Q phase balance System I and Q channel in band ripple System baseband path gain match ...

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SL1935 Table 10. Electrical Characteristics Characteristic SYNTHESISER SDA,SCL Input high voltage Input low voltage Input high current Input low current Leakage current Hysterysis SDA output voltage SCL clock rate Charge pump output current Charge pump output leakage Charge pump drive ...

Page 15

RF 9 RFB RF inputs V REF2 1K 1K TANK TANKB Oscillator inputs (pins 28, 29 and 31, 32) IFIA IFIB BIAS IFQA IFQB Baseband amplifier inputs (pins 11, 12, 25 and 23) Figure 17. Input and output interface ...

Page 16

SL1935 V ccd 2 XTAL 1 XTALCAP Reference oscillator 47K SCL/SDA ] On SDA only ] SDA/SCL (pins 3 and Output port Figure 18. Input and output interface circuits (PLL section ccd ACK V ccd ...

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Table 11. Absolute Maximum Ratings Characteristic Supply voltage SD A, SCL DC offsets All I/O port DC offsets Por t P0 current Storage temperature J unction temperature Pac kage thermal resistance, chip to case Pac kage thermal resistance, chip to ...

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SL1935 18 19. View Figure 19. Top view ...

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Figure 20. Bottom view SL1935 19 ...

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Figure 21. ...

Page 21

Purchase of Zarlink Semiconductor I 2 these components system,provided that the system conforms to the I defined by Phillips components conveys a licence under the Phillips I SL1935 2 C Patent rights to use ...

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...

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For more information about all Zarlink products Information relating to products and services furnished herein by Zarlink Semiconductor Inc. or its subsidiaries (collectively “Zarlink”) is believed to be reliable. However, Zarlink assumes no liability for errors that may appear in ...

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