74HC160PW,112 NXP Semiconductors, 74HC160PW,112 Datasheet - Page 2

IC SYNC BCD DECADE COUNT 16TSSOP

74HC160PW,112

Manufacturer Part Number
74HC160PW,112
Description
IC SYNC BCD DECADE COUNT 16TSSOP
Manufacturer
NXP Semiconductors
Series
74HCr
Datasheet

Specifications of 74HC160PW,112

Package / Case
16-TSSOP
Logic Type
Counter, Decade
Direction
Up
Number Of Elements
1
Number Of Bits Per Element
4
Reset
Asynchronous
Timing
Synchronous
Count Rate
28MHz
Trigger Type
Positive Edge
Voltage - Supply
2 V ~ 6 V
Operating Temperature
-40°C ~ 125°C
Mounting Type
Surface Mount
Mounting Style
SMD/SMT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
74HC160PW
74HC160PW
935262437112
Philips Semiconductors
FEATURES
GENERAL DESCRIPTION
The 74HC/HCT160 are high-speed Si-gate CMOS devices
and are pin compatible with low power Schottky TTL
(LSTTL). They are specified in compliance with JEDEC
standard no. 7A.
The 74HC/HCT160 are synchronous presettable decade
counters which feature an internal look-ahead carry and
can be used for high-speed counting.
Synchronous operation is provided by having all flip-flops
clocked simultaneously on the positive-going edge of the
clock (CP).
The outputs (Q
HIGH or LOW level. A LOW level at the parallel enable
QUICK REFERENCE DATA
GND = 0 V; T
December 1990
SYMBOL PARAMETER
t
t
f
C
C
PHL
PLH
max
Synchronous counting and loading
Two count enable inputs for n-bit cascading
Positive-edge triggered clock
Asynchronous reset
Output capability: standard
I
Presettable synchronous BCD decade
counter; asynchronous reset
I
PD
CC
category: MSI
propagation delay
propagation delay
maximum clock
frequency
input capacitance
power dissipation
capacitance per
package
amb
CP to Q
CP to TC
MR to Q
MR to TC
CET to TC
CP to Q
CP to TC
CET to TC
0
to Q
= 25 C; t
3
) of the counters may be preset to a
n
n
n
r
= t
f
= 6 ns
CONDITIONS
C
V
notes 1 and 2
CC
L
= 15 pF;
= 5 V
HC
19
21
21
21
14
19
21
14
61
3.5
39
TYPICAL
2
HCT
21
24
23
26
14
21
20
7
31
3.5
34
input (PE) disables the counting action and causes the
data at the data inputs (D
counter on the positive-going edge of the clock (providing
that the set-up and hold time requirements for PE are met).
Preset takes place regardless of the levels at count enable
inputs (CEP and CET).
A LOW level at the master reset input (MR) sets all four
outputs of the flip-flops (Q
of the levels at CP, PE, CET and CEP inputs (thus
providing an asynchronous clear function).
The look-ahead carry simplifies serial cascading of the
counters. Both count enable inputs (CEP and CET) must
be HIGH to count. The CET input is fed forward to enable
the terminal count output (TC). The TC output thus
enabled will produce a HIGH output pulse of a duration
approximately equal to a HIGH level output of Q
pulse can be used to enable the next cascaded stage.
The maximum clock frequency for the cascaded counters
is determined by the CP to TC propagation delay and CEP
to CP set-up time, according to the following formula:
f
max
=
-------------------------------------------------------------------------------------------------------- -
t
P max
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
MHz
pF
pF
CP to TC + t
Notes
1. C
2. For HC the condition is
dynamic power dissipation
(P
P
where:
f
f
outputs
C
pF
V
For HCT the condition is
i
o
0
0
D
CC
PD
= input frequency in MHz
L
= output frequency in MHz
D
(C
to Q
V
V
to D
1
= output load capacitance in
= C
I
I
in W):
is used to determine the
L
= supply voltage in V
= GND to V
= GND to V
3
3
PD
SU
) to be loaded into the
) to LOW level regardless
V
74HC/HCT160
(C
CC
Product specification
(CEP to CP)
L
V
2
CC
V
f
2
o
CC
CC
CC
) = sum of
2
f
i
1.5 V
f
o
0
)
. This

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