74HC590D,118 NXP Semiconductors, 74HC590D,118 Datasheet

IC COUNTER 8BIT BINARY 16-SOIC

74HC590D,118

Manufacturer Part Number
74HC590D,118
Description
IC COUNTER 8BIT BINARY 16-SOIC
Manufacturer
NXP Semiconductors
Series
74HCr
Datasheet

Specifications of 74HC590D,118

Package / Case
16-SOIC (3.9mm Width)
Logic Type
Binary Counter
Direction
Up
Number Of Elements
1
Number Of Bits Per Element
8
Reset
Asynchronous
Count Rate
61MHz
Trigger Type
Positive Edge
Voltage - Supply
2 V ~ 6 V
Operating Temperature
-40°C ~ 125°C
Mounting Type
Surface Mount
Counter Type
Binary Counters
Logic Family
74HC
Number Of Bits
8
Operating Supply Voltage
2 V to 6 V
Operating Temperature Range
- 40 C to + 125 C
Mounting Style
SMD/SMT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Timing
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
74HC590D-T
74HC590D-T
935278827118
1. General description
2. Features
3. Ordering information
Table 1.
Type number Package
74HC590N
74HC590D
74HC590PW
74HC590BQ
Ordering information
Temperature range Name
40 C to +125 C
40 C to +125 C
40 C to +125 C
40 C to +125 C
The 74HC590 is a high-speed Si-gate CMOS device and is pin compatible with Low
power Schottky TTL (LSTTL). It is specified in compliance with JEDEC standard no. 7A.
The 74HC590 is an 8-bit binary counter with a storage register and 3-state outputs. The
storage register has parallel (Q0 to Q7) outputs. The binary counter features a master
reset counter (MRC) and count enable (CE) inputs. The counter and storage register have
separate positive edge triggered clock (CPC and CPR) inputs. If both clocks are
connected together, the counter state always is one count ahead of the register. Internal
circuitry prevents clocking from the clock enable. A ripple carry output (RCO) is provided
for cascading. Cascading is accomplished by connecting RCO of the first stage to CE of
the second stage. Cascading for larger count chains can be accomplished by connecting
RCO of each stage to the counter clock (CPC) input of the following stage. If both clocks
are connected together, the counter state always is one count ahead of the register.
I
I
I
I
I
I
74HC590
8-bit binary counter with output register; 3-state
Rev. 02 — 28 April 2009
Counter and register have independent clock inputs
Counter has master reset
Complies with JEDEC standard no. 7A
Multiple package options
ESD protection:
Specified from 40 C to +85 C and from 40 C to +125 C
N
N
N
HBM JESD22-A114E exceeds 2000 V
MM JESD22-A115-A exceeds 200 V
CDM JESD22-C101C exceeds 2000 V
DIP16
SO16
TSSOP16
DHVQFN16 plastic dual in-line compatible thermal enhanced very thin
Description
plastic dual in-line package; 16 leads (300 mil)
plastic small outline package; 16 leads; body width 3.9 mm SOT109-1
plastic thin shrink small outline package; 16 leads; body
width 4.4 mm
quad flat package; no leads; 16 terminals; body
2.5
3.5
0.85 mm
Product data sheet
Version
SOT38-4
SOT403-1
SOT763-1

Related parts for 74HC590D,118

74HC590D,118 Summary of contents

Page 1

Rev. 02 — 28 April 2009 1. General description The 74HC590 is a high-speed Si-gate CMOS device and is pin compatible with Low power Schottky TTL (LSTTL specified in compliance ...

Page 2

... NXP Semiconductors 4. Functional diagram Fig 1. Functional diagram 11 CPC CPR 12 CE MRC OE 10 Fig 2. Logic symbol 74HC590_2 Product data sheet 8-bit binary counter with output register; 3-state CPC 8-BIT BINARY COUNTER 10 MRC 13 CPR 8-BIT STORAGE REGISTER 14 OE 3-STATE OUTPUTS 13 9 RCO 15 Q0 ...

Page 3

... NXP Semiconductors CPR CPC 10 MRC Fig 4. Logic diagram 74HC590_2 Product data sheet 8-bit binary counter with output register; 3-state Rev. 02 — 28 April 2009 74HC590 9 RCO 001aac543 © NXP B.V. 2009. All rights reserved ...

Page 4

... NXP Semiconductors 5. Pinning information 5.1 Pinning 74HC590 CPR CPC MRC 9 GND 8 RCO 001aaj535 Fig 5. Pin configuration DIP16 5.2 Pin description Table 2. Pin description Symbol Pin 15 GND 8 RCO 9 MRC 10 CPC CPR 74HC590_2 Product data sheet 8-bit binary counter with output register; 3-state ...

Page 5

... NXP Semiconductors 6. Functional description [1] [2] Table 3. Function table Inputs OE CPR MRC [ HIGH voltage level LOW voltage level don’t care; = LOW-to-HIGH transition; = HIGH-to-LOW transition. [2] RCO = Q0’ · Q1’ · Q2’ · Q3’ · Q4’ · Q5’ · Q6’ · Q7’ (Q0’ to Q7’ are internal outputs of the counter). ...

Page 6

... NXP Semiconductors CPC CPR MRC RCO Fig 8. Typical timing sequence 74HC590_2 Product data sheet 8-bit binary counter with output register; 3-state counter clear count inhibit Rev. 02 — 28 April 2009 74HC590 high-impedance OFF-state 001aac548 © NXP B.V. 2009. All rights reserved ...

Page 7

... NXP Semiconductors 7. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter V supply voltage CC I input clamping current IK I output clamping current OK I output current O I supply current CC I ground current ...

Page 8

... NXP Semiconductors 9. Static characteristics Table 6. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions V HIGH-level input voltage LOW-level input voltage HIGH-level output voltage all outputs RCO standard output mA 5.2 mA bus driver output I = 6.0 mA ...

Page 9

... NXP Semiconductors 10. Dynamic characteristics Table 7. Dynamic characteristics GND (ground = 0 V); for test circuit see Symbol Parameter Conditions t propagation CPC to RCO; see pd delay CPR to Qn; see LOW to HIGH MRC to RCO; see PLH propagation V CC delay enable time OE to Qn; see disable time OE to Qn; see ...

Page 10

... NXP Semiconductors Table 7. Dynamic characteristics GND (ground = 0 V); for test circuit see Symbol Parameter Conditions t hold time CE to CPC; see recovery time MRC to CPC; see rec maximum CPC or CPR; see max frequency and Figure power V = GND dissipation capacitance [ the same PHL ...

Page 11

... NXP Semiconductors 11. Waveforms RCO output Measurement points are given in V and V are the typical output voltage levels that occur with the output load Fig 9. Waveforms showing the propagation delays from the counter clock input (CPC) to ripple carry (RCO) output and the CPC pulse width Table 8 ...

Page 12

... NXP Semiconductors RCO output Measurement points are given in V and V are the typical output voltage levels that occur with the output load Fig 11. Waveforms showing the propagation delays from the master reset counter input (MRC) to output (RCO), the MRC pulse width and recovery time ...

Page 13

... NXP Semiconductors Measurement points are given in V and V are the typical output voltage levels that occur with the output load Fig 13. Waveforms showing the set-up and hold times for the count enable input (CE) to the counter clock input (CPC) Measurement points are given in ...

Page 14

... NXP Semiconductors negative positive Test data is given in Table Definitions test circuit Termination resistance should be equal to output impedance Load capacitance including jig and probe capacitance Load resistance Test selection switch. Fig 15. Test circuit for measuring switching times Table 9. Test data Supply voltage ...

Page 15

... NXP Semiconductors 12. Package outline DIP16: plastic dual in-line package; 16 leads (300 mil pin 1 index 1 DIMENSIONS (inch dimensions are derived from the original mm dimensions UNIT max. min. max. mm 4.2 0.51 3.2 inches 0.17 0.02 0.13 Note 1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included. ...

Page 16

... NXP Semiconductors SO16: plastic small outline package; 16 leads; body width 3 pin 1 index 1 DIMENSIONS (inch dimensions are derived from the original mm dimensions) A UNIT max. 0.25 1.45 mm 1.75 0.25 0.10 1.25 0.010 0.057 inches 0.069 0.01 0.004 0.049 Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. ...

Page 17

... NXP Semiconductors TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4 pin 1 index 1 DIMENSIONS (mm are the original dimensions) A UNIT max. 0.15 0.95 mm 1.1 0.25 0.05 0.80 Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. ...

Page 18

... NXP Semiconductors DHVQFN16: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 16 terminals; body 2.5 x 3.5 x 0.85 mm terminal 1 index area terminal 1 index area DIMENSIONS (mm are the original dimensions) (1) A UNIT max. 0.05 0. 0.2 0.00 0.18 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. ...

Page 19

... Release date 74HC590_2 20090428 • Modifications: The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. • Legal texts have been adapted to the new company name where appropriate. • Quick reference data incorporated in to • ...

Page 20

... Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice ...

Page 21

... NXP Semiconductors 17. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 Ordering information . . . . . . . . . . . . . . . . . . . . . 1 4 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 5 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 5.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 5.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 6 Functional description . . . . . . . . . . . . . . . . . . . 5 7 Limiting values Recommended operating conditions Static characteristics Dynamic characteristics . . . . . . . . . . . . . . . . . . 9 11 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 12 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 15 13 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 19 14 Revision history ...

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