STA027 ST Microelectronics, STA027 Datasheet

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STA027

Manufacturer Part Number
STA027
Description
SBC Codec
Manufacturer
ST Microelectronics
Datasheet

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STA027 13TR
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Features
Applications
Order codes
September 2005
Fully Integrated SBC Encoder And Decoder
Operating Modes:
– SBC encoder mode (PCM In/Serial Output)
– SBC Decoder Mode
Digital Volume
Bass & Treble Control
Serial Bitstream Input/output Interface up to
2Mbit/s
Easy Programmable ADC Input Interface
Serial PCM Output Interface (I
Formats)
PLL for Internal Clock and for Output PCM
Clock Generation
I
Low Power 2.4V CMOS Technology with 3.3V
Tolerant and Capable I/O
bluetooth AV Applications
DVD Wirless Speaker Options
2
C Control Bus
Part number
PCM input: 16, 32, 44.1, 48kHz
Channel Mode: Mono, Dual,
Stereo
Subbands: 4 OR 8
Allocation Methods:
Loudness/SNR
Serial Input
PCM Output: 16, 32, 44.1, 48kHz
STA027
2
S and other
CD00066274
Package
TQFP64
Description
STA027 is a fully integrated SBC codec targeting
wireless audio transmission such as DVD rear
channels wireless speakers, USB dongle, PC
wireless speakers. The device is fully controllable
through a standard I
Compression Engine
SBC
The SBC Subband Coding engine can be used
when high quality audio is required in wireless
applications (such as Bluetooth). SBC is an audio
coding system specially designed for Bluetooth
AV applications to obtain high quality audio at
medium bit rates, and having a low computational
complexity. SBC uses 4 or 8 subbands, adaptive
bit allocation algorithm, and simple adaptive block
PCM quantizers..
Wireless Audio Dongle
PC Wireless Speakers
Generic Compressed Audio LinkS
Wireless Headphone/Headsets
2
TQFP64
C bus.
Packing
SBC CODEC
Tube
PRODUCT PREVIEW
STA027
www.st.com
Rev 1
1/44
44

Related parts for STA027

STA027 Summary of contents

Page 1

... PC Wireless Speakers ■ Generic Compressed Audio LinkS ■ Wireless Headphone/Headsets Description STA027 is a fully integrated SBC codec targeting wireless audio transmission such as DVD rear channels wireless speakers, USB dongle, PC wireless speakers. The device is fully controllable through a standard and other ...

Page 2

... Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.2 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 4 Host register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 4.1 Register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 5 Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5.1 Version registers description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5.1.1 VERSION : . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5.1.2 IDENT : . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5.1.3 SOFT_VERSION : . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5.2 PLL_AUDIO_CONFIGURATION registers description . . . . . . . . . . . . . . . . . 16 5.2.1 PLL_AUDIO_PEL_192 : . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 5.2.2 PLL_AUDIO_PEH_192 : 5.2.3 PLL_AUDIO_NDIV_192 : . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 5.2.4 PLL_AUDIO_XDIV_192 : . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 5.2.5 PLL_AUDIO_MDIV_192 : . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 5.2.6 PLL_AUDIO_PEL_176 : . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 5.2.7 PLL_AUDIO_PEH_176 : 5.2.8 PLL_AUDIO_NDIV_176 : . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 5.2.9 PLL_AUDIO_XDIV_176 : . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 5.2.10 PLL_AUDIO_MDIV_176 : . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 5.3 PLL_SYSTEM_CONFIGURATION registers description . . . . . . . . . . . . . . . 19 5.3.1 PLL_SYSTEM_PEL_50 : . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 5.3.2 PLL_SYSTEM_PEH_50 : . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 5.3.3 PLL_SYSTEM_NDIV_50 : . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 2/ CD00066274 STA027 ...

Page 3

... STA027 5.3.4 PLL_SYSTEM_XDIV_50 : . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 5.3.5 PLL_SYSTEM_MDIV_50 : . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 5.3.6 PLL_SYSTEM_PEL_42_5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 5.3.7 PLL_SYSTEM_PEH_42_5 : . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 5.3.8 PLL_SYSTEM_NDIV_42_5 : . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 5.3.9 PLL_SYSTEM_XDIV_42_5 : . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 5.3.10 PLL_SYSTEM_MDIV_42_5 : . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 5.4 I2Sout_CONFIGURATION registers description . . . . . . . . . . . . . . . . . . . . . . 23 5.4.1 OUTPUT_CONF : 5.4.2 PCM_DIV : . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 5.4.3 PCM_CONF : . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 5.4.4 PCM_CROSS : . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 5.5 GPSO_CONFIGURATION registers description . . . . . . . . . . . . . . . . . . . . . . 25 5.5.1 OUTPUT_CONF : . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 5.5.2 GPSO_CONF : . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 5.6 I2Sin_CONFIGURATION registers description . . . . . . . . . . . . . . . . . . . . . . . 27 5.6.1 INPUT_CONF : 5.6.2 I_AUDIO_CONFIG_1 5.6.3 I_AUDIO_CONFIG_2 : . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 5.6.4 I_AUDIO_CONFIG_3 : . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 5.7 SDI_CONFIGURATION registers description . . . . . . . . . . . . . . . . . . . . . . . . 29 5.7.1 POL_REQ : . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 5.7.2 INPUT_CONF : 5.7.3 I_AUDIO_CONFIG_1 : . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 5.8 COMMAND registers description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 5.8.1 SOFT_RESET : . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 5.8.2 CK_CMD : 5.8.3 DEC_SEL : . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 5.8.4 RUN : . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 5.8.5 CRC_IGNORE : . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 5 ...

Page 4

... TTL Schmitt Trigger Inpud Pad Buffer, 3V capable . . . . . . . . . . . . . . . . . . . . 41 7.4 TTL Inpud Pad Buffer, 3V capable with Pull- 7.5 TTL Schmitt Trigger Bidir Pad Buffer, with Pull-up, 4mA, with slew rate control / 3V capable 42 7.6 TTL Input Pad Buffer, 3V capable, with pull down . . . . . . . . . . . . . . . . . . . . . 42 8 Package Informations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 9 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 4/ CD00066274 STA027 ...

Page 5

... PLL REG BANK OSCK ENCODER SDO ADC I/F I/F R STA027 DECODER 2 BT SDI I S OUT MODULE I/F I/F STA027 CD00066274 1 Typical application circuit and block diagram BSO_LRCK BSO_DATA SDO I/F BSO_BCK GPSO_CK GPSO_SDO GPSO I/F GPSO_REQ BCKO 2 PCM OUTPUT I S OUT SDO BUFFER I/F LRCKO AUDIO ...

Page 6

... I GPSO bit clock O GPSO request signal I/O GPIODATA0 I/O GPIODATA1 I/O GPIODATA2 I/O GPIODATA3 I/O GPIODATA4 I/O GPIODATA5 CD00066274 STA027 Source/Dest From DSP From DSP From DSP To MCU From MCU From MCU From MCU From ADC From ADC From ADC To DAC/ADC To DAC To DAC To DAC To MCU From MCU ...

Page 7

... STA027 Table 1. pin description PIN Pin Name 34 IODATA6 35 IODATA7 44 IODATA8 45 IODATA9 46 IODATA10 47 IODATA11 48 IODATA12 49 IODATA13 50 IODATA14 51 IODATA15 HANDSHAKE SIGNALS 59 RQST 60 STB LINK 63 SCL 64 SDA MISCELLANEOUS 15 -RESET 16 -TESTEN 17 XTI 18 XTO 25 CLKOUT 38 FILT1 40 FILT0 POWER SUPPLY 5 VDD_1 6 VSS_1 10 VDD_2 11 VSS_2 23 VCC_1 24 VSS_3 ...

Page 8

... LRCK1 13 BCKI 14 SDI Parameter CD00066274 Source/Dest IODATA12 47 IODATA11 46 IODATA10 45 IODATA9 44 IODATA8 43 VSS_6 42 VCC_2 41 PLL_GND 40 FILT0 39 PLL_VCC 38 FILT1 37 VSS_5 36 VDD_4 35 IODATA7 34 IODATA6 33 IODATA5 D00AU1227 Value 85 STA027 Unit °C/W ...

Page 9

... STA027 3 Electrical Specification 3.1 Absolute maximum ratings Table 3. Absolute Maximum Ratings Symbol V Digital Power Supply at 2.5V (nominal Digital Power Supply at 3.3V (nominal Analog Supply Voltage at 2.5V (nominal Voltage on input pins (3.3V pads Storage Temperature stg T Operative ambient temp op T Operating Junction Temperature j 3 ...

Page 10

... Note: power measurements refer to encoder mode. 10/44 Test Condition I = Xma ol Test Condition V = 0V; pin numbers and 26 Test Condition Sampling_freq ≤24 kHz = DD Sampling_freq ≤32 kHz Sampling_freq ≤48 kHz CD00066274 STA027 Min. Typ. Max. Unit 0.2 0.8 0.4V V 0.85 Min. Typ. Max. Unit µA ...

Page 11

... STA027 4 Host register The following table gives a description of STA027 register list. The STA027 device includes 256 I described. The undocumented registers are reserved or unused. These registers must never be accessed (in Read or in Write mode). The Read-Only registers must never be written We can split the data flux in different time periods (see following diagram) meanwhile host registers can be read or written : ● ...

Page 12

... OUTPUT_CONF 0x67 103 PCM_DIV 0x68 104 PCM_CONF 0x69 105 PCM_CROSS 0x66 102 OUTPUT_CONF 0x6A 106 GPSO_CONF 0x5A 90 INPUT_CONF 0x5B 91 I_AUDIO_CONFIG_1 0x5C 92 I_AUDIO_CONFIG_2 0x5D 93 I_AUDIO_CONFIG_3 CD00066274 STA027 Name Type When ...

Page 13

... STA027 Table 9. register map by function Register function SDI_CONFIGURATION COMMAND STATUS MIX_CONFIGURATION TONE_CONFIGURATION Hex Dec 0x59 89 POL_REQ 0x5A 90 INPUT_CONF 0x5B 91 I_AUDIO_CONFIG_1 0x10 16 SOFT_RESET 0x3A 58 CK_CMD 0x55 85 DEC_SEL 0x56 86 RUN 0x52 82 CRC_IGNORE 0x53 83 MUTE 0x57 87 SKIP 0x58 88 PAUSE 0xCC 204 STATUS_MODE 0xCD 205 ...

Page 14

... SOFT_VERSION : b7 b6 Address : 0xD3 (211) Type : RO - DWT Software Reset : X Description : The SOFT_VERSION register is Read-only and it is used to identify the software running on the IC. 14/ CD00066274 STA027 ...

Page 15

... STA027 5.2 PLL_AUDIO_CONFIGURATION registers description 5.2.1 PLL_AUDIO_PEL_192 : b7 b6 Address : 0xDC (220) Type : RW - DEC Software Reset : 58 Description : This register must contain a PEL value that enables the audio PLL to generate a frequency of ofact*192 kHz for the PCMCK.See table 1, 2 & 3. ofact is the oversampling factor needed by the DAC (ofac==246 or ofac==384). ...

Page 16

... This register must contain a MDIV value that enables the audio PLL to generate a frequency of ofact*192 kHz for the PCMCK.See table 1, 2 & 3. Default value at soft reset assume : – ofact == 256 – external crystal provide a CRYCK running at 14.31818 MHz 16/ CD00066274 STA027 ...

Page 17

... STA027 5.2.6 PLL_AUDIO_PEL_176 : b7 b6 Address : 0xE1 (225) Type : RW - DEC Software Reset : 54 Description : This register must contain a PEL value that enables the audio PLL to generate a frequency of ofact*176 kHz for the PCMCK.See table 1, 2 & 3. Default value at soft reset assume : – fact == 256 – ...

Page 18

... PCMCK.See table 1,2 & 3. Default value at soft reset assume : – ofact == 256 – external crystal provide a CRYCK running at 14.31818 MHz 5.3 PLL_SYSTEM_CONFIGURATION registers description 5.3.1 PLL_SYSTEM_PEL_50 : b7 b6 Address : 0xE6 (230) 18/ CD00066274 STA027 ...

Page 19

... STA027 Type : RW - DEC Software Reset : 0 Description : This register must contain a PEL value that enables the system PLL to generate a frequency of 50 MHz for the SYSCK. See table 4. Default value at soft reset assume : – external crystal provide a CRYCK running at 14.31818 MHz 5.3.2 PLL_SYSTEM_PEH_50 : b7 b6 ...

Page 20

... This register must contain a PEL value that enables the system PLL to generate a frequency of 42.5 MHz for the SYSCK.See table 4. Default value at soft reset assume : – external crystal provide a CRYCK running at 14.31818 MHz 20/ CD00066274 STA027 ...

Page 21

... STA027 5.3.7 PLL_SYSTEM_PEH_42_5 : b7 b6 Address : 0xE7 (231) Type : RW - DEC Software Reset : 223 Description : This register must contain a PEH value that enables the system PLL to generate a frequency of 42.5 MHz for the SYSCK.See table 4. Default value at soft reset assume : – external crystal provide a CRYCK running at 14.31818 MHz 5 ...

Page 22

... Note that this embedded default configuration can be retrieved by user thanks to following setting : – PCM_DIV = 3; – PCM_CONF = 0; – PCM_CROSS = 0; 5.4.2 PCM_DIV : Address : 0x67 (103) Type : RW - DEC 22/ DV5 DV4 DV3 CD00066274 STA027 DV2 DV1 DV0 ...

Page 23

... STA027 Software Reset : 0 Description : If OUTPUT_CONF == 1, configure the divider to generate the bit clock of the I called BCK0, from PCMCK. according the following relation : BCKO = PCMCK / 2 * (PCM_DIV+1) 5.4.3 PCM_CONF : CO6 Address : 0x68 (104) Type : RW - DEC Software Reset : 0 Description : If OUTPUT_CONF == 1, configure the I Table 10. . Bit fields bits mode (16 slots transmitted) ...

Page 24

... Left channel is duplicated on both output channels. Right channel is duplicated on both output channels. Right and left channels are toggled Configuration of gpso : 0 : take embedded default configuration configure gpso from register GPSO_CONF. CD00066274 CR1 Comment b2 b1 0C2 OC1 Comment STA027 b0 CR0 b0 OC0 ...

Page 25

... STA027 Table 12. Bit fields OC1 OC2 Note: that embedded default configuration for GPSO can be retrieved by user thanks to following setting : – GPSO_CONF = b00000011; Note: that embedded default configuration for PCM block is described at previous chapter. 5.5.2 GPSO_CONF : b7 b6 CF7 CF6 Address : 0x6A (106) Type : RW - DEC ...

Page 26

... CF2 0 : data provided on falling edge & stable on rising edge data provided on rising edge & stable on falling edge 26/ Sin Input thanks to following registers, else disable CF5 CF4 CF3 2 Sin interface. Comment CD00066274 STA027 CF2 CF1 CF0 ...

Page 27

... STA027 Table 14. Bit fields Polarity of LR clock LRCK : CF3 0 : negative 1 : positive Start value of LRCK : combined with CF3, this bit enable user to determine left/right CF4 couple according to the following table. CF[7:5] Reserved : to be set to 0. Table 15. CF3 5.6.3 I_AUDIO_CONFIG_2 : b7 b6 LR7 LR6 ...

Page 28

... CF1 = 1 (MSB), value must be set to bit position of the first bit of data within the LRCK phase. Note: that range of value for this bit position is [0:31]. Length-1 of the data. Max value is 31. Reserved : to be set CD00066274 Comment STA027 b0 b0 ...

Page 29

... STA027 5.7.3 I_AUDIO_CONFIG_1 : Address : 0x5B (91) Type : RW - DEC Software Reset : 0 Description : If INPUT_CONF == 1, this register is used to configure BSB bit clock Table 17. . Bit Polarity of bit clock BS_BCK : CF0 0 : data provided on falling edge & stable on rising edge data provided on rising edge & stable on falling edge. ...

Page 30

... When the external device wants to end the external configuration period, it must write the value 1 inside the register RUN: this is the run command that starts the decoding process (see I). 30/ SINE (test mode chip alive) SBC decoder ADC/GPSO SBC encoder SDI/GPSO SBC encoder ADC/SDO SBC encoder CD00066274 STA027 Mode ...

Page 31

... STA027 5.8.5 CRC_IGNORE : b7 b6 Address : 0x52 (82) Type : RW - ABO Software Reset : 0 Description : For decoders having CRC abilities (see each decoder configuration), if set to 0 enable the check of CRC, if set to 1 disable the check of the CRC. 5.8.6 MUTE : b7 b6 Address : 0x53 (83) Type : RW - ABO Software Reset : 0 Description : For decoders having MUTE abilities (see each decoder configuration), if set to 0 disable the mute of the decoder, if set to 1 enable the mute of the decoder ...

Page 32

... This register give the type of the currently decoded bitstream. 5.9.2 STATUS_CHANS_NB : b7 b6 Address : 0xCD (205) Type : RO - EDF Software Reset : 0 Description : This register gives the number of channel currently decoded. 5.9.3 STATUS_SF : b7 b6 Address : 0xCE (206) Type : RO - EDF Software Reset : 0 Description : 32/ CD00066274 STA027 ...

Page 33

... STA027 This register gives the index of the sampling frequency of the stream currently decoded. Note that sampling frequency indexes are given by table 5 5.9.4 STATUS_FE : b7 b6 Address : 0x6F (111) Type : RO - AEC Software Reset : 0 Description : This register give the status of the synchronization process according following table. ...

Page 34

... This register specifies the left attenuation (in dB) on rigth channel. 5.10.4 MIX_DRA Address : 0x7E (126) Type : RW - ABO Software Reset : 0 Description : This register specifies the direct right attenuation (in dB). 34/44 diseable mix/volume control volume control mono to stereo (up-mix) stereo to mono (down-mix CD00066274 STA027 Mode ...

Page 35

... STA027 5.10.5 MIX_DRB Address : 0x7F (127) Type : RW - ABO Software Reset : 0 Description : This register specifies the rigth attenuation (in dB) on left channel. 5.11 TONE_CONFIGURATION registers description 5.11.1 TONE_ON Address : 0x75 (117) Type : RW - ABO Software Reset : 0 Description : This register enables/diseables (1/0) the tone control. 5.11.2 TONE_FCUTH : b7 b6 ...

Page 36

... This register specifies the gain on high frequencies: gain (in Db)=(TONE_GAINL-12)*1.5. Value of register from 0 to 24. 5.11.6 TONE_GAIN_ATTEN : b7 b6 Address : 0x7A (122) Type : RW - ABO Software Reset : 0 Description : This register specifies the attenuation on global spectrum: gain (in dB)=- TONE_GAIN_ATTEN*1.5. Value of register from 0 to 12. 36/ CD00066274 STA027 ...

Page 37

... STA027 6 TABLES Table 21. values to configure audio PLL for ofact==256. This table give values to configure the audio PLL according CRYCK so that to generate a PCMCK == 256*SF. Register PLL_AUDIO_PEL_192 PLL_AUDIO_PEH_192 PLL_AUDIO_NDIV_192 PLL_AUDIO_XDIV_192 PLL_AUDIO_MDIV_192 PLL_AUDIO_PEL_176 PLL_AUDIO_PEH_176 PLL_AUDIO_NDIV_176 PLL_AUDIO_XDIV_176 PLL_AUDIO_MDIV_176 Table 22. values to configure audio PLL for ofact==384 This table give values to configure the audio PLL according CRYCK so that to generate a PCMCK == 384*SF ...

Page 38

... CRYCK in MHz CRYCK in MHz 14.31818 14.7456 58 85 187 157 0 157 CRYCK in MHz CRYCK in MHz 14.31818 14.7456 152 126 100 223 135 Frequency 48 kHz 44.1 kHz 32 kHz 96 kHz 88.2 kHz STA027 ...

Page 39

... STA027 Table 25. index of the Sampling Frequency Index 6.1 Notations ABO : After BOot (see I). AEC : After External Config (see I). BCK: Bit ClocK BSA: BitStream input interface in Audio mode. BSB: BitStream input interface in Burst mode. BS: BitStream input interface. BYPASSA : decoder BYPASS an Audio stream. ...

Page 40

... TTL Schmitt Trigger Inpud Pad Buffer, 3V capable Pin numbers:17, 60 D98AU905 7.4 TTL Inpud Pad Buffer, 3V capable with Pull-Up Pin numbers:15 D98AU907 40/ CD00066274 STA027 INPUT PIN MAX LOAD Z 100pF OUTPUT INPUT PIN CAPACITANCE PIN IO TBD IO INPUT PIN CAPACITANCE A TBD INPUT PIN ...

Page 41

... STA027 7.5 TTL Schmitt Trigger Bidir Pad Buffer, with Pull-up, 4mA, with slew rate control / 3V capable Pin numbers: 26, 27, 28, 31, 32, 33, 34, 35, 44, 45, 46, 47, 48, 49, 50, 51 D00AU1150 7.6 TTL Input Pad Buffer, 3V capable, with pull down Pin numbers: 12, 13, 14 D00AU1222 ...

Page 42

... TQFP64 ( 1.4mm) 0.0031 TQFP64 CD00066274 OUTLINE AND MECHANICAL DATA 0.08mm ccc Seating Plane C K 0051434 E STA027 ...

Page 43

... STA027 9 Revision history Date Revision 1-sept-2005 1 Initial release. CD00066274 9 Revision history Changes 43/44 ...

Page 44

... Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America 44/44 All other names are the property of their respective owners © 2005 STMicroelectronics - All rights reserved STMicroelectronics group of companies www.st.com CD00066274 STA027 ...

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