STA323W ST Microelectronics, STA323W Datasheet
STA323W
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STA323W Summary of contents
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... Channels can be provid two full-bridges, providing up to 2x20W of power. The IC can also be configured as a single paralelled full-bridge capable of high-current oper- ation and 1x40W output. Also provided in the STA323W are a full assort- STA323W Package PowerSO36 (Slug Down) Tape & Reel DataShee Rev ...
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... STA323W ment of digital processing features. This includes programmable 28-bit biquads (EQ) per channel, and bass/treble tone control. Automodes™ enable a time-to-market advantage by substantially reducing the amount of software development needed for certain functions. This includes Auto Volume loudness, preset volume curves, preset EQ settings, etc. New advanced AM radio inerference reduction modes. ...
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... Half Bridge Half Bridge OUT2B OUT1A Half Bridge OUT1B Half Bridge Half Bridge OUT2A Half Bridge OUT2B STA323W De- Bass T reble Emphasis Filter Filt Mix If CxT Bass Boost /Cut If DEMP = reble Boost/Cut Channel 1 Channel 1 Channel 2 Channel 2 Channel 1 ...
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... STA323W Figure 8. BLOCK DIAGRAMS (refer to Stereo Application Circuit REG V SS Vcc Sign GND REG VL 3.3V CONFIG GNDCLEAN SCL SDA RESET BICKI SDI LRCKI 550pF XTI 7250 20pF VDDA 3.3V GNDA VDD 3.3V GND Figure 9. Pin Description DataSheet4U.com 4/41 4 DataSheet U .com C30 ...
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... Analog Ground Analog Ground Analog Supply Analog Supply 3.3 SDI_12 I²S Serial Data Channels 1 & 2 LRCKI I²S Left/Right Clock, BICKI I²S Serial Clock Digital Ground Digital Ground Digital Supply Digital Supply 3.3V VSS DIGITAL 5V Regulator referred to +Vcc VCCDIGITAL 5V Regulator referred to ground STA323W DESCRIPTION DataShee 5/41 ...
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... STA323W Table 3. ABSOLUTE MAXIMUM RATINGS Symbol V 3.3V I/O Power Supply DD_3.3 V Voltage on input pins i V Voltage on output pins o T Storage Temperature stg T Ambient Operating Temperature amb V DC Supply Voltage CC V Maximum voltage on pins 20 MAX Table 4. THERMAL DATA Symbol R Thermal resistance Junction to case (thermal pad) ...
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... PWRDN = 0 DataSheet4U.com Vcc=30V; Tri-state Input pulse width = 50% Duty; Switching Frequency = 384Khz filters; No Load THD = 10 8Ω 18V L S THD = 8Ω 18V L S STA323W = 25°C unless otherwise amb Min. Typ. Max. Unit 200 270 mΩ µ 100 ...
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... STA323W I C BUS SPECIFICATION The STA323W supports the I2C protocol. This protocol defines any device that sends data on to the bus as a transmitter and any device that reads the data as a receiver. The device that controls the data trans- fer is known as the master and the other as the slave. The master always starts the transfer and provides the serial clock for synchronization ...
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... A STOP condition terminates communication between STA323W and the bus master. 6.1.4 Data Input During the data input the STA323W samples the SDA signal on the rising edge of clock SCL. For correct device operation the SDA signal must be stable during the rising edge of the clock and the data can change only when the SCL line is low ...
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... STA323W again responds with an acknowledgement. The master then initiates another START condition and sends the device select code with the RW bit set to 1. The STA323W ac- knowledges this and then responds by sending one byte of data. The master then terminates the transfer by generating a STOP condition ...
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... C5B2 C5B1 MPCC11 MPCC10 MPCC9 MPCC3 MPCC2 MPCC1 RES RES RES RES RES RES FDRC11 FDRC10 FDRC9 FDRC3 FDRC2 FDRC1 FAULT STA323W D1 D0 MCS0 SAI0 OM0 HPB MPCV OCFG0 MMute MV1 MV0 C1V0 C2V0 C3V0 AMEQ0 AMAME PEQ0 C1TCB C2TCB BTC0 ...
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... R R R/W 0 The STA323W will support sample rates of 32kHz, 44.1kHz, 48Khz, 88.2kHz, and 96kHz. Therefore the internal clock will be: 32.768Mhz for 32kHz ■ 45.1584Mhz for 44.1khz, 88.2kHz, and 176.4kHz ■ 49.152Mhz for 48kHz, 96kHz, and 192kHz ■ The external clock frequency provided to the XTI pin must be a multiple of the input sample frequency (fs). ...
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... R/W 1 The on-chip STA323W Power Output block provides feedback to the digital controller using inputs to the Power Control block. The TWARN input is used to indicate a thermal warning condition. When TWARN is asserted (set to 0) for a period greater than 400ms, the power control block will force an adjustment to the modulation limit in an attempt to eliminate the thermal warning condition ...
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... Right Justified LRCLK SCLK SDATA For example, SAI=1110 and SAIFB=1 would specify Right-Justified 16-bit data, LSB-First. Table 10 below lists the serial audio input formats supported by STA323W as related to BICKI = 32/48/ 64fs, where the sampling rate fs = 32/44.1/48/88.2/96/176.4/192 kHz. Table 9. First Bit Selection Table SAIFB 0 1 Note: Serial input and output formats are specified distinctly ...
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... Left-Justified 20bit Data X Left-Justified 18bit Data X Left-Justified 16bit Data X Right-Justified 24bit Data X Right-Justified 20bit Data X Right-Justified 18bit Data X Right-Justified 16bit Data STA323W S 15bit Data S 23bit Data S 20bit Data S 18bit Data 2 S 16bit Data 2 S 16bit Data S 24bit Data S 20bit Data S 18bit Data DataShee ...
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... STA323W Figure 13. LRCKI BICKI SDI 7.3.1 Delay Serial Clock Enable BIT R/W RST 5 R/W 0 7.3.2 Channel Input Mapping BIT R/W RST 6 R R/W 1 Each channel received via I2S can be mapped to any internal processing channel via the Channel Input Mapping registers. This allows for flexibility in processing. The default settings of these registers map each I2S input channel to its corresponding processing channel ...
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... ZDE 0 0 7.5.1 High-Pass Filter Bypass BIT R/W 0 R/W The STA323W features an internal digital high-pass filter for the purpose of DC Blocking. The purpose of this filter is to prevent DC signals from passing through a DDX® amplifier. DC signals can cause speaker damage. 7.5.2 De-Emphasis BIT R/W 1 R/W By setting this bit to HIGH, or one (1), de-emphasis will implemented on all channels. DSPB (DSP Bypass, Bit D2, CFA) bit must be set to 0 for De-emphasis to function ...
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... STA323W 7.5.3 DSP Bypass BIT R/W RST 2 R/W 0 Setting the DSPB bit bypasses all the EQ and Mixing functionality of the STA323W Core. 7.5.4 Post-Scale Link BIT R/W RST 3 R/W 0 Post-Scale functionality is an attenuation placed after the volume control and directly before the conver- sion to PWM. Post-Scale can also be used to limit the maximum modulation index and therefore the peak current ...
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... Setting the MPC bit corrects the DDX-2060/2100/2160 power device at high power. This mode will lower the THD full DDX-2060 DDX 7.6.3 AM Mode Enable BIT R/W 3 R/W The STA323W features a DDX frequency range of AM radio. This mode is intended for use when DDX active AM tuner. The SNR of the DDX than the SNR of AM radio. 7.6.4 PWM Speed Mode BIT R/W ...
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... R/W 1 The STA323W includes a soft volume algorithm that will step through the intermediate volume values at a predetermined rate when a volume change occurs. By setting SVE=0 this can be bypassed and volume changes will jump from old to new value directly. This feature is only available if individual channel volume bypass bit is set to ‘ ...
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... Power device. This register has to be written to ® power device for normal operation. DataSheet4U.com MV5 MV4 MV3 C1V5 C1V4 C1V3 STA323W DESCRIPTION DESCRIPTION DESCRIPTION MMUTE MV2 MV1 C1V2 C1V1 0 0 DataShee D0 MV0 1 ...
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... Volume Description The volume structure of the STA323W consists of individual volume registers for each of the three chan- nels and a master volume register, and individual channel volume trim registers. The channel volume set- tings are normally used to set the maximum allowable digital gain and to hard-set gain differences between certain channels ...
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... Mode (Biquad 1-4) User Programmable Preset EQ – PEQ bits Auto Volume Controlled Loudness Curve Not used MVOL 0.5dB 256 Steps (Standard) MVOL Auto Curve 30 Steps MVOL Auto Curve 40 Steps MVOL Auto Curve 50 Steps STA323W Volume +48dB +47.5dB +47dB … +0.5dB 0dB -0.5dB … ...
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... STA323W Table 20. AutoMode Gain Compression/Limiters AMGC (1... 7.9.2 AMPS – AutoMode Auto Prescale BIT R/W RST 0 R/W 0 7.9.3 Register – AutoMode AM/Pre-Scale/Bass Management Scale (Address 0Ch XO3 XO2 0 0 7.9.3.1AutoMode AM Switching Enable BIT R/W RST 0 R/W 0 3…1 R/W 000 Table 21. AutoMode AM Switching Frequency Selection AMAM (2 ...
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... Bass-Boost #1 Bass-Boost #2 Bass-Boost #3 Loudness 1 (least boost) Loudness 2 Loudness 3 Loudness 4 Loudness 5 Loudness 6 Loudness 7 Loudness 8 Loudness 9 Loudness 10 Loudness 11 Loudness 12 Loudness 13 Loudness 14 Loudness 15 Loudness 16 (most boost) STA323W User 80 Hz 100 Hz 120 Hz 140 Hz 160 Hz 180 Hz 200 Hz 220 Hz 240 Hz 260 Hz 280 Hz 300 Hz 320 Hz 340 Hz 360 ...
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... By setting the CxBO bit to ‘1’, each channel can be individually controlled binary operation mode. Also, there is the capability to map each channel independently onto any of the two limiters available within the STA323W or even not map it to any limiter at all (default mode). Table 24. Channel Limiter Mapping Selection CxLS (1,0) ...
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... D5 D4 L1A1 L1A0 1 0 PWM Output From Channel 1 Channel 2 Channel 3 Not used BTC3 BTC2 BTC1 Boost/Cut -12dB -12dB … -4dB -2dB 0dB +2dB +4dB … +12dB +12dB +12dB L1R3 L1R2 L1R1 STA323W D0 BTC0 1 DataShee D0 L1R0 0 27/41 ...
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... Control Description The STA323W includes 2 independent limiter blocks. The purpose of the limiters is to automatically re- duce the dynamic range of a recording to prevent the outputs from clipping in anti-clipping mode actively reduce the dynamic range for a better listening environment (such as a night-time listening mode, which is often needed for DVDs ...
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... Saturation LxR (3...0) Release Rate dB/ms 0000 0.5116 0001 0.1370 0010 0.0744 0011 0.0499 0100 0.0360 0101 0.0299 0110 0.0264 0111 0.0208 1000 0.0198 1001 0.0172 1010 0.0147 1011 0.0137 1100 0.0134 1101 0.0117 1110 0.0110 1111 0.0104 STA323W Fast DataShee Slow 29/41 ...
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... STA323W 7.12.6Anti-Clipping Mode Table 29. Limiter Attack Threshold Selection (AC-Mode) LxAT (3...0) 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Table 30. Limiter Release Threshold Selection (AC-Mode). LxRT (3...0) 0000 0001 0010 0011 0100 ...
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... By default, all pre-scale factors are set to 7FFFFFh. 8.3 POST-SCALE The STA323W provides one additional multiplication after the last interpolation stage and before the dis- tortion compensation on each channel. This is a 24-bit signed fractional multiplier. The scale factor for this multiplier is loaded into RAM using the same I2C registers as the biquad coefficients and the mix. All channels can use the same settings as channel 1 by setting the post-scale link bit ...
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... Channel #2 from EQ After a mix is achieved, STA323W also provides the capability to implement crossver filters on all channels corresponding to 2.1 bass management solution. Channels 1-2 use a 1st order high-pass filter and chan- nel 3 uses a 2nd order low-pass filter corresponding to the setting of the XO bits of I2C register 0Ch 000, user specified crossover filters are used ...
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... C2B19 C2B13 C2B12 C2B11 C2B5 C2B4 C2B3 C1B21 C1B20 C1B19 STA323W CFA2 CFA1 CFA0 C1B18 C1B17 C1B16 C1B10 C1B9 C1B8 C1B2 ...
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... STA323W 8.6.9 1.1.9Coefficient a1 Data Register Bits 15...8 (Address 1Eh C3B15 C3B14 0 0 8.6.10Coefficient a1 Data Register Bits 7...0 (Address 1Fh C3B7 C3B6 0 0 8.6.11Coefficient a2 Data Register Bits 23...16 (Address 20h C4B23 C4B22 0 0 8.6.12Coefficient a2 Data Register Bits 15...8 (Address 21h) ...
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... Write Control Register (Address 26h Coefficients for EQ, Mix and Scaling are handled internally in the STA323W via RAM. Access to this RAM is available to the user via an I tion. First register contains the coefficient base address, five sets of three registers store the values of the 24-bit coefficients to be written or that were read, and one contains bits used to control the read or write of the coefficient (s) to RAM ...
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... When using this technique, the 8-bit address would specify the address of the biquad b1 coefficient (e. 10, 15, …, 45 decimal), and the STA323W will generate the RAM addresses as offsets from this base value to write the complete set of coefficient data. ...
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... Channel 1 – Mix 1 39h Channel 1 – Mix 2 3Ah Channel 2 – Mix 1 3Bh Channel 2 – Mix 2 3Ch Channel 3 – Mix 1 3Dh Channel 3 – Mix 2 3Eh UNUSED 3Fh UNUSED STA323W Coefficient Default C1H10 (b1/2) 000000h C1H11 (b2) 000000h C1H12 (a1/2) 000000h C1H13 (a2) 000000h C1H14 (b0/2) 400000h C1H20 000000h … ...
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... STA323W 8.11 Variable Max Power Correction (Address 27h-28h): MPCC bits determine the 16 MSBs of the MPC compensation coefficient. This coefficient is used in place of the default coefficient when MPCV = 1. Table 35 MPCC15 MPCC14 0 0 MPCC7 MPCC6 1 1 8.12 Fault Detect Recovery (Address 2Bh-2Ch): FDRC bits specify the 16-bit Fault Detect Recovery time delay. When FAULT is asserted, the TRISTATE output will be immediately asserted low and held low for the time period specified by this constant ...
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... DataSheet4U.com STA323W OUTLINE AND MECHANICAL DATA PowerSO-36 0096119 C DataShee 39/41 ...
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... STA323W Table 37. Revision History Date July 2005 January 2006 DataSheet4U.com 40/41 4 DataSheet U .com Revision 1 First Issue 2 Modified in page 12/41 the table Configuration Register A (Address 00h) DataSheet4U.com Description of Changes DataShee ...
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... Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America DataSheet4U.com 4 DataSheet U .com DataSheet4U.com The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners DDX is a trademark of Apogee tecnology inc. © 2006 STMicroelectronics - All rights reserved STMicroelectronics group of companies www.st.com STA323W 41/41 ...