SCC68692 Philips, SCC68692 Datasheet
SCC68692
Available stocks
Related parts for SCC68692
SCC68692 Summary of contents
Page 1
... SCC68692 Dual asynchronous receiver/transmitter (DUART) Product specification Supersedes data of 1995 May 01 IC19 Data Handbook Philips Semiconductors INTEGRATED CIRCUITS 1998 Sep 04 ...
Page 2
... In addition, a flow control capability is provided to disable a remote DUART transmitter when the receiver buffer is full. Also provided on the SCC68692 are a multipurpose 6-bit input port and a multipurpose 8-bit output port. These can be used as general purpose I/O ports or can be assigned specific functions (such as clock inputs or status/interrupt outputs) under program control ...
Page 3
... OP3 OP5 17 OP7 INTRN 22 GND Figure 1. Pin Configurations PARAMETER DIP40 PLCC44 DIP40 PLCC44 3 Product specification SCC68692 PLCC TOP VIEW PIN/FUNCTION INTRN IP3 IP1 OP6 ...
Page 4
... RECEIVE HOLDING REG (3) RECEIVE SHIFT REGISTER MRA1, 2 CRA SRA CHANNEL B (AS ABOVE) INPUT PORT CHANGE OF STATE DETECTORS (4) IPCR ACR OUTPUT PORT FUNCTION SELECT LOGIC OPCR OPR Figure 2. Block Diagram 4 Product specification SCC68692 TxDA RxDA TxDB RxDB 6 IP0-IP5 8 OP0-OP7 V CC GND SD00145 ...
Page 5
... I Power Supply: +5V supply input. CC GND 20 I Ground 1998 Sep 04 NAME AND FUNCTION pull-up device supplying current. CC pull-up device supplying current. CC pull-up device supplying current. CC pull-up device supplying current Product specification SCC68692 ...
Page 6
... TTL input levels CMOS input levels TTL input levels CMOS input levels 6 Product specification SCC68692 LIMITS UNIT UNIT Min Typ Max 0.8 V 2.0 V 2 –0.5 –10 +10 A –75 0 ...
Page 7
... For X1/CLK this swing is between 0.4V and 4.4V. All time measurements are referenced at input voltages of 0.8V and 2.0V and output voltages of 0.8V and 2.0V, as appropriate. 3. Typical values are at +25 C, typical supply voltages, and typical processing parameters. 1998 Sep 04 PARAMETER PARAMETER (1X) (1X) 7 Product specification SCC68692 LIMITS UNIT UNIT 3 Min Typ Max 200 ns ...
Page 8
... Operation to 0MHz is assured by design. Minimum test frequency is 2.0MHz. 12. See UART application note for power down currents less than 5 A. BLOCK DIAGRAM The SCC68692 DUART consists of the following eight major sections: data bus buffer, operation control, interrupt control, timing, communications Channels A and B, input port and output port. ...
Page 9
... OPERATION Transmitter The SCC68692 is conditioned to transmit data when the transmitter is enabled through the command register. The SCC68692 indicates to the CPU that it is ready to accept a character by setting 1998 Sep 04 the TxRDY bit in the status register. This condition can be programmed to generate an interrupt request at OP6 or OP7 and INTRN ...
Page 10
... The slave stations, with receivers that are normally disabled, examine the received data stream and ‘wake up’ the CPU (by setting RxRDY) 10 Product specification SCC68692 ...
Page 11
... This output is normally asserted by setting OPR[0] and negated by resetting OPR[0]. MR1A[ causes RTSAN to be negated upon receipt of a valid start bit if the Channel A FIFO is full. 11 Product specification SCC68692 The reserved WRITE (WRN = 0) Mode Register A (MR1A, MR2A) Clock Select Register A (CSRA) ...
Page 12
... THR (if any) are completely transmitted (including the programmed number of stop bits previously issued transmitter disable is pending. This feature can be used to automatically terminate the transmission as follows: 1. Program the auto-reset mode: MR2[5]=1 12 Product specification SCC68692 ...
Page 13
... When using the above procedure with the transmitter in the underrun condition, the issuing of the transmitter disable must be delayed from the loading of a single, or last, character until the TxRDY becomes active again after the character is loaded. 13 Product specification SCC68692 ...
Page 14
... BIT 5 BIT 4 BIT 3 COUNTER/TIMER DELTA IP3 INT 0 = Off See Table Product specification SCC68692 BIT 2 BIT 1 BIT 0 PARITY BITS PER TYPE CHARACTER Even Odd BIT 2 BIT 1 BIT 0 STOP BIT LENGTH 0.813 8 = 1.563 ...
Page 15
... MR2A, except that all control actions apply to the Channel B receiver and transmitter and the corresponding inputs and outputs. Table 3. Baud Rate CSRA[7:4] ACR[ 0000 0001 0010 134.5 0011 0100 0101 15 Product specification SCC68692 BIT 2 BIT 1 BIT 0 IP2 IP1 IP0 0 = Low 0 = Low 0 = Low 1 = High 1 = High 1 = High BIT 2 BIT 1 BIT 0 ...
Page 16
... CRB – Channel B Command Register CRB is a register used to supply commands to Channel B. Multiple commands can be specified in a single write to CRB as long as the commands are non-conflicting, e.g., the ‘enable transmitter’ and ‘reset transmitter’ commands cannot be specified in a single command word. 16 Product specification SCC68692 ...
Page 17
... In the counter mode, the output remains High until terminal count is reached, at which time it goes Low. The output returns to the High state when the counter is stopped by a stop counter command. Note that this output is not masked by the contents of the IMR. 17 Product specification SCC68692 ...
Page 18
... ISR – the true status will be provided regardless of the contents of the IMR. The contents of this register are initialized to H‘00’ when the DUART is reset. 18 Product specification SCC68692 CLOCK SOURCE External (IP2) TxCA – 1x clock of Channel A transmitter TxCB – ...
Page 19
... In the counter mode, the current value of the upper and lower 8 bits of the counter (CTU, CTL) may be read by the CPU recommended that the counter be stopped when reading to prevent 19 Product specification SCC68692 ...
Page 20
... DUART responds to a valid interrupt acknowledge cycle. t RES SD00028 Figure 3. Reset Timing t CSC RWS t CSW NOT DATA VALID VALID t CSD t DAL t DCR t DAT Figure 4. Bus Timing (Read Cycle) 20 Product specification SCC68692 t RWH DAH SD00147 ...
Page 21
... NOTE: DACKN low requires two rising edges of X1 clock after CSN is low. 1998 Sep 04 t CSC RWS CSD t DCW t DAT Figure 5. Bus Timing (Write Cycle) t CSC CSD t DAL t t DCR DAH Figure 6. Interrupt Cycle Timing 21 Product specification SCC68692 t RWH t CSW DAH SD00148 DAT SD00149 ...
Page 22
... This point represents noise margin that assures true switching has occurred. Beyond this level, the effects of external circuitry and test environment are pronounced OL and can greatly affect the resultant measurement. 1998 Sep OLD DATA t PD Figure 7. Port Timing RDN WRN INTERRUPT OUTPUT Figure 8. Interrupt Timing 22 Product specification SCC68692 NEW DATA SD00150 +0. SD00090 ...
Page 23
... TO 150 K X2 4pF TYPICAL CRYSTAL SPECIFICATION 2 – 4MHZ ): 12 – 32pF L PARALLEL RESONANT, FUNDAMENTAL MODE Figure 9. Clock Timing 1 BIT TIME ( CLOCKS) t TXD TxD t TCS Figure 10. Transit Timing 23 Product specification SCC68692 + INTERNAL CLOCK DRIVERS SD00137 SD00146 ...
Page 24
... BREAK D3 START D4 STOP BREAK BREAK Figure 12. Transmitter Timing STATUS DATA D5 WILL D2 BE LOST Figure 13. Receiver Timing 24 Product specification SCC68692 SD00093 WILL D6 NOT BE TRANSMITTED OPR( SD00118 D6, D7, D8 WILL BE LOST STATUS DATA STATUS DATA D3 D4 RESET BY COMMAND SD00119 ...
Page 25
... When the transmitter is controlling this pin, its meaning is not RTS at all. It is, rather, that the transmitter has finished sending its last data byte. Programming the MP0 pin Product specification SCC68692 BIT 9 ADD#2 1 BIT 9 BIT 9 ADD STATUS DATA ...
Page 26
... This change affects all receivers and transmitters on the DUART. See “Extended baud rates for SCN2681, SCN68681, SCC2691, SCC2692, SCC68681 and SCC2698B” in application notes elsewhere in this publication –5 at 9600 baud. 26 Product specification SCC68692 BRG Test ACR[ ACR[ 4,800 7,200 880 880 ...
Page 27
E – PIN # 1 0.100 (2.54) BSC 2.087 (53.01) – D – 2.038 (51.77) 0.070 (1.78) 0.050 (1.27) – T – SEATING PLANE 0.023 (0.58 0.010 (0.254) 0.015 (0.38) NOTES: 0.098 ...
Page 28
... Philips Semiconductors Dual asynchronous receiver/transmitter (DUART) DIP40: plastic dual in-line package; 40 leads (600 mil) 1998 Sep 04 28 Product specification SCC68692 SOT129-1 ...
Page 29
... Philips Semiconductors Dual asynchronous receiver/transmitter (DUART) PLCC44: plastic leaded chip carrier; 44 leads 1998 Sep 04 29 Product specification SCC68692 SOT187-2 ...
Page 30
... Philips Semiconductors 811 East Arques Avenue P.O. Box 3409 Sunnyvale, California 94088–3409 Telephone 800-234-7381 Philips Semiconductors 1998 Sep 04 [1] Copyright Philips Electronics North America Corporation 1998 Document order number: 30 Product specification SCC68692 All rights reserved. Printed in U.S.A. Date of release: 09-98 9397 750 04361 ...