SC26C94C1N Philips Semiconductors, SC26C94C1N Datasheet

Page 1

... Dog” timer for each receiver COMMERCIAL INDUSTRIAL V = +5V +10 +5V +10 + – + SC26C94C1N SC26C94A1N SC26C94C1A SC26C94A1A 1 Product specification SC26C94 DACKN IACKN RQN I/O0a–d I/O1a–d I/O2a–d I/O3a–d TDa-d SD00158 DWG # DWG # o C SOT240-1 ...

Page 2

... Philips Semiconductors Quad universal asynchronous receiver/transmitter (QUART) PIN CONFIGURATIONS 48-Pin Dual-In-Line Package 1 48 X1/CLK 2 47 TXDD 3 46 RXDD 4 45 IRQN WRN CEN 15 34 RDN 16 33 ...

Page 3

... Philips Semiconductors Quad universal asynchronous receiver/transmitter (QUART) BLOCK DIAGRAM 8 BUS BUFFER D0–D7 OPERATION CONTROL RDN WRN ADDRESS DECODE CEN 6 A0–A5 R/W CONTROL RESET DACKN TIMING 2 CRYSTAL X1/CLK OSCILLATOR POWER UP-DOWN X2 LOGIC BAUD RATE GENERATOR DUART CD TXDC TXDD SAME AS RXDC DUART AB RXDD ...

Page 4

... Philips Semiconductors Quad universal asynchronous receiver/transmitter (QUART) PIN DESCRIPTION MNEMONIC TYPE CEN I Chip Select: Active low input that, in conjunction with RDN or WRN, indicates that the host MPU is trying to access a QUART register. CEN must be inactive when IACKN is asserted. A5:0 I Address Lines: These inputs select a 26C94 register to be read or written by the host MPU. ...

Page 5

... Philips Semiconductors Quad universal asynchronous receiver/transmitter (QUART) 1 Table 1. QUART Registers A5:0 READ (RDN = Low) 000000 Mode Register a (MR0a, MR1a, MR2a) 000001 Status Register a (SRa) 000010 Reserved 000011 Receive Holding Register a (RxFIFOa) 000100 Input Port Change Reg ab (IPCRab) 000101 Interrupt Status Reg ab (ISRab) ...

Page 6

... FIFO or pop an empty FIFO do not affect the count. Baud Rate Generator The baud rate generator used in the QUART is the same as that used in other Philips Semiconductors industry standard UARTs. It provides 18 basic Baud rates from 50 baud to 38,400 baud. It has been enhanced to provide to provide other baud rates up to 230,400 baud based on a 3.6364MHz clock ...

Page 7

... Philips Semiconductors Quad universal asynchronous receiver/transmitter (QUART) Timer Mode In the timer mode a symmetrical square wave is generated whose half period is equal in time to division of the selected counter/timer clock frequency by the 16-bit number loaded in the CTLR CTUR. Thus, the frequency of the counter/timer output will be equal to the counter/timer clock frequency divided by twice the value of the CTUR CTLR ...

Page 8

... Philips Semiconductors Quad universal asynchronous receiver/transmitter (QUART) mean five bytes may be loaded; 111 means 7, etc. Eight positions will be indicated by a binary 111 and the FIFO empty bit will be set. Receiver The receiver accepts serial data on the RxD pin, converts the serial ...

Page 9

... Philips Semiconductors Quad universal asynchronous receiver/transmitter (QUART) position, it considers it an address bit and loads that character to the RxFIFO and set the RxRDY bit in the status register. The user would usually set the receiver interrupt to occur on RxRDY as well. (All characters whose parity bits are set to 0 will be ignored). The local processor at the slave station will read the ‘ ...

Page 10

... Philips Semiconductors Quad universal asynchronous receiver/transmitter (QUART) The interrupt arbitration logic insures that the interrupt with the numerically largest bid value will be the only source driving the interrupt bus at the end of the arbitration period. The arbitration period follows the period of the X1 clock. The maximum speed is 4.0MHz higher speed X1 clock is used then the X1 clock “ ...

Page 11

... Philips Semiconductors Quad universal asynchronous receiver/transmitter (QUART) Interrupt Context The channel number of the winning “bid” is used by the address decoders to provide data from the interrupting UART channel via a set of Global pseudo-registers. The interrupt Global pseudo-registers are: 1. Global Interrupting Byte Count 2. Global Interrupting Channel 3 ...

Page 12

... Philips Semiconductors Quad universal asynchronous receiver/transmitter (QUART) Table 4. Register Bit Formats, Duart ab. [duplicated for Duart cd] Bit 7 Bit 6 Bit 5 MR0 (Mode Register 0) Rx Watchdog RxINT2 bit Timer 0 = off These bits should normally be set MR1 (Mode Register 1) RxRTS RxINT1 Select Error Mode* ...

Page 13

... Threshold Calculation” description. MR1[6] operates with MR0[6] to prevent the receiver from bidding until a particular fill level is attained. For software compatibility this bit is designed to emulate the RxFIFO interrupt function of previous Philips Semiconductors UARTs. MR1[5] – Error Mode Select This bit selects the operating mode of the three FIFOed status bits (received break, FE, PE). In the character mode, status is provided on a character-by-character basis ...

Page 14

... Philips Semiconductors Quad universal asynchronous receiver/transmitter (QUART) In the “Block Error” mode the ORing of the error status bits and the presentation of them to the status register takes place as the bytes enter the RxFIFO. This allows an indication of problem data when the error occurs after the leading bytes have been received. In the character mode the error bits are presented to the status register when the corresponding byte is at the top of the FIFO ...

Page 15

... Philips Semiconductors Quad universal asynchronous receiver/transmitter (QUART) finished processing the present character and is ready to search for the start bit of the next character. Table 5. Bit Rate Generator Characteristics Crystal or Clock = 3.6864MHz NORMAL RATE ACTUAL 16X (BAUD) CLOCK (kHz) 50 0.8 75 1.2 110 1.759 134.5 2 ...

Page 16

... Philips Semiconductors Quad universal asynchronous receiver/transmitter (QUART) Table 6. Baud Rate BRG RATE = LOW CSR[7:4] ACR[ ACR[ 110 134 200 300 600 1,200 1,050 ...

Page 17

... Philips Semiconductors Quad universal asynchronous receiver/transmitter (QUART) The selected set of rates is available for use by the receiver and transmitter. ACR[6:4] – Counter/Timer Mode and Clock Source Select This field selects the operating mode of the counter/timer and its clock source (see Table 4). ...

Page 18

... Philips Semiconductors Quad universal asynchronous receiver/transmitter (QUART) ISR[1] – Receiver Ready or FIFO Full Channel a See the description of ISR[5]. The channel ‘a’ receiver operation is the same as channel ‘b’. ISR[0] – Transmitter Ready Channel a See the description of ISR[4]. Channel “a” transmitter operates in the same manner as channel “ ...

Page 19

... Philips Semiconductors Quad universal asynchronous receiver/transmitter (QUART) Table 8. Register Bit Formats, I/O Section Bit 7 Bit 6 Bit 5 IPCR (Input Port Change Register ab) The lower four bits replicate the lower four bits of the IPR. The upper four bits reads state of Change detectors. Change detectors are enabled in ACR[3:0]. (DUART ab) ...

Page 20

... Philips Semiconductors Quad universal asynchronous receiver/transmitter (QUART) I/O Port Control Channel B (IOPCRB) IOPCRb[7:6] IOPCR[xx] IOPCR[xx] Pin Control Bits Pin Control Bits I/O3B 00 = input IPR(7), TxC output OPRab( output TxC 16x 11 = output TxC 1x I/O Port Control Channel C (IOPCRC) IOPCRc[7:6] IOPCR[xx] IOPCR[xx] Pin Control Bits ...

Page 21

... Philips Semiconductors Quad universal asynchronous receiver/transmitter (QUART) Global Interrupt Byte Count (GIBC) 00000 5 The GIBC is not an actual register but simply outputs the interrupting UART’s transmit or receive byte counter value. The count, accurate at the time IACKN asserts, is captured in the CIR. The high order 5 bits are read as ‘ ...

Page 22

... Philips Semiconductors Quad universal asynchronous receiver/transmitter (QUART) DC ELECTRICAL CHARACTERISTICS SYMBOL PARAMETER SYMBOL PARAMETER V Input low voltage Input high voltage (except X1/CLK) Input high voltage (except X1/CLK Input high voltage (X1/CLK Output Low voltage OL V Output High voltage (except OD outputs) ...

Page 23

... Philips Semiconductors Quad universal asynchronous receiver/transmitter (QUART) AC ELECTRICAL CHARACTERISTICS SYMBOL SYMBOL FIGURE FIGURE Reset timing t 7 Reset pulse width RES I/O Port timing t 8 I/O input setup time before RDN Low I/O input hold time after RDN High PH I/O output valid from WRN High ...

Page 24

... Philips Semiconductors Quad universal asynchronous receiver/transmitter (QUART) AC ELECTRICAL CHARACTERISTICS 10%, unless otherwise specified. Limits shown as nn/nn refer to Commercial/Industrial temperature range. Single A CC numbers apply to both ranges. NO. NO. FIGURE FIGURE 1 2 A[5:0] Setup time to RDN WRN Low 2 2 A[5:0] Hold time from RDN WRN Low ...

Page 25

... Philips Semiconductors Quad universal asynchronous receiver/transmitter (QUART) AC ELECTRICAL CHARACTERISTICS Commercial/Industrial temperature range. Single numbers apply to both ranges. NO. NO. FIGURE FIGURE CHARACTERISTIC CHARACTERISTIC 1 3 D[7:0] Valid after IACKN Low 2 3 DACKN Low after IACKN Low 3 3 D[7:0] floating after IACKN High 4 3 DACKN High after IACKN High ...

Page 26

... Philips Semiconductors Quad universal asynchronous receiver/transmitter (QUART) HOLD EN BYTE COUNTER TRANSMITTER OFFSET CORRECTION LOGIC IACK BYTE COUNT UPDCIR READ GIBC READ CIR READ CICR D7 D6 INTRAN–INTRDN, I/O0a–I/O3d D0–D7, TxDa–TxDh, I/O0a–I/O3d 1995 May 1 INTBUSN7:0 INVERTING LATCHES ...

Page 27

... Philips Semiconductors Quad universal asynchronous receiver/transmitter (QUART) RESET RDN t PS I/O as Input I/O PINS MUST BE STABLE FOR NON-CHANGING BUS DATA DURING THE READ. CEN WRN I/O as Output NOTE: I/O PIN DATA IS NOT LATCHED WRN 1 INTERRUPT OUTPUT RDN 1 INTERRUPT OUTPUT NOTES: 1. INCLUDES I/O WHEN USED AS TxRDY or RxDY/FFULL OUTPUTS AS WELL AS IRQN. ...

Page 28

... Philips Semiconductors Quad universal asynchronous receiver/transmitter (QUART) t CLK t CTC X1/CLK CTCLK RxC TxC 24pF FOR and C2 should be chosen according to the crystal manufacturer’s specification. C1 and C2 values will include any parasitic capacitance of the wiring 3.6864MHz NOTES: C1 and C2 should be based on manufacturer’s specification. ...

Page 29

... Philips Semiconductors Quad universal asynchronous receiver/transmitter (QUART) RxC (1X INPUT) RxD TxD D1 TRANS- MITTER ENABLED TxRDY (SR2) MR0(5: WRN CTSN (I/O0) 2 RTSN (I/O1) CR[7:4] = 1010 NOTES: 1. TIMING SHOWN FOR MR2[ TIMING SHOWN FOR MR2[ 1995 May RXS RXH Figure 12. Receive Clock Timing ...

Page 30

... Philips Semiconductors Quad universal asynchronous receiver/transmitter (QUART) RxD D1 D2 RECEIVER ENABLED RxRDY (SR0) D2 FFULL (SR1) RxRDY/ FFULL ISR(1) RDN OVERRUN (SR4) 1 RTS I/O1 I/ (CR[7:4] = 1010) NOTES; 1. TIMING SHOWN FOR MR1[ DEFAULT: I/O1 IS RTS AND IOPCR(5:4) 01 MASTER STATION BIT 9 ADD#1 1 TxD TRANSMITTER ...

Page 31

... Philips Semiconductors Quad universal asynchronous receiver/transmitter (QUART) INTERRUPT NOTES The following is a brief description of the new QUART “Bidding” interrupt system, interrupt vector and the use of the Global registers. The new features of the QUARTs have been developed to greatly reduce the microprocessor time required to service uart interrupts. ...

Page 32

... Philips Semiconductors Quad universal asynchronous receiver/transmitter (QUART) through the most significant 6 bits. The result of this is that the channel value does not ’bid’. However the logic is such that other parts of the bid being equal the condition of the highest channel will be captured in CIR. The increasing order of the channels Thus channel D is the ” ...

Page 33

... Philips Semiconductors Quad universal asynchronous receiver/transmitter (QUART) addressed register. The generation of DACKN begins with the start of a bus cycle (Read, Write or Interrupt Acknowledge) and then requires two edges of the X1 clock plus typically 70ns for its assertion. In this mode the writing of data to the QUART registers occurs on the falling edge of DACKN or the rising edge of the combination of CEN and WRN which ever occurs first ...