MC74HC390ADTR2 ON Semiconductor, MC74HC390ADTR2 Datasheet

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MC74HC390ADTR2

Manufacturer Part Number
MC74HC390ADTR2
Description
IC COUNTER RPPL DUAL 4ST 16TSSOP
Manufacturer
ON Semiconductor
Series
74HCr
Datasheet

Specifications of MC74HC390ADTR2

Logic Type
Divide-by-N
Number Of Elements
2
Number Of Bits Per Element
4
Reset
Asynchronous
Count Rate
50MHz
Trigger Type
Negative Edge
Voltage - Supply
2 V ~ 6 V
Operating Temperature
-55°C ~ 125°C
Mounting Type
Surface Mount
Package / Case
16-TSSOP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Direction
-
Timing
-
MC74HC390A
Dual 4-Stage Binary Ripple
Counter with ÷ 2 and ÷ 5
Sections
High−Performance Silicon−Gate CMOS
inputs are compatible with standard CMOS outputs; with pullup
resistors, they are compatible with LSTTL outputs.
composed of a divide−by−two and a divide−by−five section. The
divide−by−two and divide−by−five counters have separate clock
inputs, and can be cascaded to implement various combinations of ÷ 2
and/or ÷ 5 up to a ÷ 100 counter.
transitions of the clock input. A separate, asynchronous reset is
provided for each 4−bit counter. State changes of the Q outputs do not
occur simultaneously because of internal ripple delays. Therefore,
decoded output signals are subject to decoding spikes and should not
be used as clocks or strobes except when gated with the Clock of the
HC390A.
Features
*For additional information on our Pb−Free strategy and soldering details, please
© Semiconductor Components Industries, LLC, 2008
May, 2008 − Rev. 4
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
The MC74HC390A is identical in pinout to the LS390. The device
This device consists of two independent 4−bit counters, each
Flip−flops internal to the counters are triggered by high−to−low
No 7A
Output Drive Capability: 10 LSTTL Loads
Outputs Directly Interface to CMOS, NMOS, and TTL
Operating Voltage Range: 2.0 to 6.0 V
Low Input Current: 1 mA
High Noise Immunity Characteristic of CMOS Devices
In Compliance with the Requirements Defined by JEDEC Standard
Chip Complexity: 244 FETs or 61 Equivalent Gates
Pb−Free Packages are Available*
1
16
16
See detailed ordering and shipping information in the package
dimensions section on page 2 of this data sheet.
16
16
1
1
1
1
ORDERING INFORMATION
A
L, WL
Y, YY
W, WW
G
G
(Note: Microdot may be in either location)
http://onsemi.com
CASE 751B
CASE 948F
SOEIAJ−16
TSSOP−16
DT SUFFIX
CASE 648
CASE 966
N SUFFIX
D SUFFIX
F SUFFIX
SOIC−16
PDIP−16
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
= Pb−Free Package
Publication Order Number:
16
16
1
1
16
1
MC74HC390AN
MC74HC390A/D
DIAGRAMS
AWLYYWWG
16
1
MARKING
HC390AG
AWLYWW
74HC390A
ALYWG
ALYWG
390A
HC
G

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MC74HC390ADTR2 Summary of contents

Page 1

... Chip Complexity: 244 FETs or 61 Equivalent Gates • Pb−Free Packages are Available* *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. © Semiconductor Components Industries, LLC, 2008 May, 2008 − Rev. 4 http://onsemi.com PDIP− ...

Page 2

... ORDERING INFORMATION Device MC74HC390AN MC74HC390ANG MC74HC390AD MC74HC390ADG MC74HC390ADR2 MC74HC390ADR2G MC74HC390ADTR2 MC74HC390ADTR2G MC74HC390AF MC74HC390AFG MC74HC390AFEL MC74HC390AFELG †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. *This package is inherently Pb−Free ...

Page 3

... Plastic DIP: – 10 mW/_C from 65_ to 125_C SOIC Package: – 7 mW/_C from 65_ to 125_C TSSOP Package: − 6.1 mW/_C from 65_ to 125_C For high frequency or heavy load considerations, see Chapter 2 of the ON Semiconductor High−Speed CMOS Data Book (DL129/D). RECOMMENDED OPERATING CONDITIONS Î Î Î Î ...

Page 4

... Maximum Input Capacitance in 1. For propagation delays with loads other than 50 pF, see Chapter 2 of the ON Semiconductor High−Speed CMOS Data Book (DL129/D). Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î ...

Page 5

... NOTE: Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor High−Speed CMOS Data Book (DL129/D). INPUTS Clock A (Pins 1, 15) and Clock B (Pins 4, 15) Clock A is the clock input to the ÷ ...

Page 6

CLOCK CLOCK RESET CLOCK A RESET TEST CIRCUIT TEST POINT OUTPUT DEVICE UNDER TEST *Includes all probe and ...

Page 7

Each half of the MC54/74HC390A has independent ÷ 2 and ÷ 5 sections (except for the Reset function). The ÷ 2 and ÷ 5 counters can be connected to give BCD or bi−quinary (2−5) count sequences. If Output Q A ...

Page 8

0.25 (0.010) M −A− −T− SEATING PLANE 0.25 (0.010 PACKAGE DIMENSIONS PDIP−16 N ...

Page 9

K 16X REF 0.10 (0.004) 0.15 (0.006 L PIN 1 IDENT. 1 0.15 (0.006 −V− C 0.10 (0.004) −T− SEATING D PLANE 16X 0.36 PACKAGE DIMENSIONS TSSOP−16 DT SUFFIX CASE ...

Page 10

... Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada Fax: 303− ...

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