ACS8520T Semtech, ACS8520T Datasheet

no-image

ACS8520T

Manufacturer Part Number
ACS8520T
Description
Synchronous Equipment Timing Source (SETS) for Stratum 3/4E/4 and SMC Systems
Manufacturer
Semtech
Datasheet
The ACS8520 is a highly integrated, single-chip solution
for the Synchronous Equipment Timing Source (SETS)
function in a SONET or SDH Network Element. The device
generates SONET or SDH Equipment Clocks (SEC) and
Frame Synchronization clocks. The ACS8520 is fully
compliant with the required international specifications
and standards.
The device supports Free-run, Locked and Holdover
modes. It also supports all three types of reference clock
source: recovered line clock, PDH network, and node
synchronization. The ACS8520 generates independent
SEC and BITS/SSU clocks, an 8 kHz Frame
Synchronization clock and a 2 kHz Multi-Frame
Synchronization clock.
Two ACS8520 devices can be used together in a Master/
Slave configuration mode allowing system protection
against a single ACS8520 failure.
A microprocessor port is incorporated, providing access to
the configuration and status registers for device setup
and monitoring. The ACS8520 supports IEEE 1149.1
JTAG boundary scan.
The user can choose between OCXO or TCXO to define the
Stratum and/or Holdover performance required.
Figure 1 Block Diagram of the ACS8520 SETS
Revision 3.02/October 2005 © Semtech Corp.
Description
ADVANCED COMMUNICATIONS
Block Diagram
ADVANCED COMMUNICATIONS
2 x AMI
10 x TTL
2 x PECL/LVDS
Programmable;
64/8 kHz (AMI)
2 kHz
4 kHz
N x 8 kHz
1.544/2.048 MHz
6.48 MHz
19.44 MHz
25.92 MHz
38.88 MHz
51.84 MHz
77.76 MHz
155.52 MHz
TRST
TMS
TDO
TCK
TDI
Selection
Monitors
14 x SEC
1149.1
Control
IEEE
JTAG
Input
Port
and
Generator
OCXO or
Selector
Selector
Clock
TCXO
Chip
T4
T0
T4 DPLL/Freq. Synthesis
T0 DPLL/Freq. Synthesis
Divider, 1/n
Divider, 1/n
n = 1 to 2
n = 1 to 2
Priority
Table
Optional
Optional
14
14
Register Set
PFD
PFD
[5]
Microprocessor
FINAL
Digital
Digital
FINAL
Loop
Filter
Loop
Filter
Page 1
Port
Features
DTO
DTO
Synchronous Equipment Timing Source for
Suitable for Stratum 3, 4E, 4 and SONET Minimum
Clock (SMC) or SONET/SDH Equipment Clock (SEC)
applications
Meets Telcordia 1244-CORE
GR-253
specifications
Accepts 14 individual input reference clocks, all with
robust input clock source quality monitoring.
Simultaneously generates nine output clocks, plus
two Sync pulse outputs
Absolute Holdover accuracy better than 3 x 10
(manual), 7.5 x 10
stability defined by choice of external XO
Programmable PLL bandwidth, for wander and jitter
tracking/attenuation, 0.1 Hz to 70 Hz in 10 steps
Automatic hit-less source switchover on loss of input
Microprocessor interface - Intel, Motorola, Serial,
Multiplexed, or boot from EPROM
Output phase adjustment in 6 ps steps up to ±200 ns
IEEE 1149.1 JTAG Boundary Scan
Single 3.3 V operation. 5 V tolerant
Available in LQFP 100 package
Lead (Pb) - free version available (ACS8520T), RoHS
and WEEE compliant.
[17]
(feedback)
Stratum 3/4E/4 and SMC Systems
Frequency
Frequency
T0 APLL
TO APLL
T4 APLL
Dividers
(output)
Dividers
, and ITU-T G.813
-14
(instantaneous); Holdover
Output
Ports
TO1
to
TO7
TO8
TO9
TO10
TO11
&
&
ACS8520 SETS
F8520P_001BLOCKDIA_03
[19]
[11]
T08: AMI
TO9: E1/DS1
Outputs
T01-TO7:
E1/DS1 (2.048/
1.544 MHz)
and frequency
multiples:
1.5 x, 2 x, 3 x
4 x, 6 x, 12 x
16 x and 24 x
E3/DS3
2 kHz
8 kHz
and OC-N* rates
TO10: 8 kHz
(FrSync)
TO11: 2 kHz
(MFrSync)
OC-N* rates =
OC-1 51.84 MHz
OC-3 155.52 MHz
and derivatives:
6.48 MHz
19.44 MHz
25.92 MHz
38.88 MHz
51.84 MHz
77.76 MHz
155.52 MHz
311.04 MHz
Stratum 3 and
Options Ι and ΙΙ
DATASHEET
www.semtech.com
-10

Related parts for ACS8520T

Related keywords