ACS8525T Semtech, ACS8525T Datasheet
ACS8525T
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ACS8525T Summary of contents
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... PLL “Locked” and “Acquisition” bandwidths individually selectable from 18 Serial interface for device set-up Single 3.3 V operation I/O compatible Operating temperature (ambient) of -40 to +85°C Available in LQFP 64 package Lead (Pb)-free version available (ACS8525T), RoHS and WEEE compliant DPLL1 DPLL2 MUX 2 ...
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... Aligning Phase of MFrSync and FrSync Outputs to Phase of Sync Inputs......................................................................... 34 Power-On Reset............................................................................................................................................................................... 35 Serial Interface................................................................................................................................................................................ 35 Register Map........................................................................................................................................................................................... 38 Register Organization ..................................................................................................................................................................... 38 Multi-word Registers ............................................................................................................................................................. 38 Register Access ..................................................................................................................................................................... 38 Interrupt Enable and Clear ................................................................................................................................................... 38 Defaults.................................................................................................................................................................................. 38 Register Descriptions ............................................................................................................................................................................. 42 Revision 3.01/August 2005 © Semtech Corp. Table of Contents FINAL Page 2 ACS8525 LC/P DATASHEET Page www.semtech.com ...
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... Input/Output Timing ..................................................................................................................................................................... 105 Package Information ............................................................................................................................................................................ 106 Thermal Conditions....................................................................................................................................................................... 107 Application Information ........................................................................................................................................................................ 108 References ............................................................................................................................................................................................ 109 Abbreviations ........................................................................................................................................................................................ 109 Notes ..................................................................................................................................................................................................... 110 Trademark Acknowledgements ........................................................................................................................................................... 110 Revision Status/History ....................................................................................................................................................................... 111 Ordering Information ............................................................................................................................................................................ 112 Disclaimers.................................................................................................................................................................................... 112 Contacts......................................................................................................................................................................................... 112 Revision 3.01/August 2005 © Semtech Corp. FINAL Page 3 ACS8525 LC/P DATASHEET Page www.semtech.com ...
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... AGND1 2 IC1 3 AGND2 4 VA1+ 5 INTREQ 6 REFCLK 7 DGND1 8 VD1+ 9 VD2+ 10 DGND2 1 11 DGND3 12 VD3+ 13 SRCSW 14 VA2+ 15 AGND3 16 IC2 Revision 3.01/August 2005 © Semtech Corp. FINAL ACS8525 LC/P Page 4 ACS8525 LC/P DATASHEET 48 PORB 47 SCLK 46 VDD6 45 VDD5 44 CSB 43 SDI 42 CLKE 41 TMS 40 DGND5 39 VDD4 38 VDD3 37 TRST 36 VDD2 ...
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... I/O 5 INTREQ O 6 REFCLK I 13 SRCSW I Revision 3.01/August 2005 © Semtech Corp. FINAL Type - Supply Voltage: Digital supply to gates in analog section, +3.3 Volts ±10%. - Supply Voltage: Digital supply for differential output pins 19 and 20, +3.3 Volts ±10%. - Digital Supply for +5 Volts Tolerance to Input Pins. Connect to +5 Volts (± ...
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... I 52 SDO SONSDHB I Revision 3.01/August 2005 © Semtech Corp. FINAL Type TTL/CMOS Output Reference: 8 kHz Frame Sync output. TTL/CMOS Output Reference: 2 kHz Multi-Frame Sync output. LVDS/PECL Output Reference: Programmable, default 38.88 MHz, LVDS. PECL/LVDS Input Reference: Programmable, default 19.44 MHz, PECL. ...
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... DPLL bandwidth. This ensures that the overall system performance still maintains the advantage of consistent behavior provided by the digital approach. Revision 3.01/August 2005 © Semtech Corp. FINAL The DPLLs are clocked by the external Oscillator module (TCXO or XO) so that the Free-run or Digital Holdover frequency stability is only determined by the stability of the external oscillator module ...
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... SEC1 TTL and SEC2 TTL ports are on pins SEC1 and SEC2. SEC1 DIFF (Differential) port uses pins SEC1POS and SEC1NEG, similarly SEC2DIFF uses pins SEC2POS and SEC2NEG. Revision 3.01/August 2005 © Semtech Corp. FINAL Table 4 gives details of the input reference ports, showing the input technologies and the range of frequencies supported on each port ...
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... The DivN function is defined as: Revision 3.01/August 2005 © Semtech Corp. FINAL DivN = “Divide 1”, i. the dividing factor used for the division of the input frequency, and has a value where integer from 1 to 15624 inclusive ...
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... Source Leaky Bucket Response Alarm Revision 3.01/August 2005 © Semtech Corp. FINAL occur over a greater time period but still sufficiently close together to overcome the decay, the alarm will be triggered eventually. If events occur at a rate which is not sufficient to overcome the decay, the alarm will not be triggered ...
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... Leaky Bucket Configuration in each case). Revision 3.01/August 2005 © Semtech Corp. FINAL The default setting is shown in the following 4 1.0 secs Fast Activity Monitor Anomalies on the selected clock have to be detected as they occur and the PLL must be temporarily isolated until the clock is once again pure ...
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... When an automatic selection is required, the force_select_reference_source register LSB 4 bits (force_select_SEC_input) must be set to all zeros or all ones. Revision 3.01/August 2005 © Semtech Corp. FINAL The Priority Table register cnfg_ref_selection_priority, occupying three 8-bit register addresses (Reg. 19, 1A and 1C), is organized as one 4-bit word per input SEC port. ...
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... A well designed system would have Master and Slave clock from the clock sync cards aligned to within a few nanoseconds. In which case a complete system using the Semtech SETS clock card parts (ACS8530, ACS8520 or ACS8510) and this Line Card part would be fully compliant to GR-1244-CORE conditions due to the low frequency range and bandwidth set at the clock card end ...
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... MHz. If DPLL2 is enabled, it locks to the 8 kHz from DPLL1. This is because all of the frequencies of operation of DPLL2 can be Revision 3.01/August 2005 © Semtech Corp. FINAL divided to 8 kHz and this will ensure synchronization of frequencies, from 8kHz upwards, within the two DPLLs. ...
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... Phase Build-out and any phase offset programmed into the device. Hence, the DPLL1 77M Forward DFS and the DPLL1 77M Output DFS blocks are locked in frequency but may be offset in phase. Revision 3.01/August 2005 © Semtech Corp. FINAL DPLL2_frequency DPLL1_freq_to_APLL2 Forward ...
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... Digital outputs is relatively high, because they do not pass through an APLL for jitter filtering. The minimum level of jitter is when DPLL1 is in analog feedback mode, Revision 3.01/August 2005 © Semtech Corp. FINAL when the p-p jitter will be approximately 13 ns (equivalent to a period of the DFS clock). The maximum jitter is generated when in digital feedback mode, when the total is approximately 18 ns ...
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... Factor Programmability” next. 4. PFD settings - these affect the input phase error to the Loop filter and relate to jitter and wander tolerance. See “Phase/Frequency/Lock Detection” on page 18. Revision 3.01/August 2005 © Semtech Corp. FINAL 5. Phase compensation functions - See “Phase Compensation Functions” on page 19. ...
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... Phase/Frequency/Lock Detection Two main types of detector are used in the ACS8525: Phase and frequency detectors, and Phase Loss/Lock detectors. Revision 3.01/August 2005 © Semtech Corp. FINAL Phase and Frequency Detectors There are two multi-phase and frequency detectors, one for each DPLL. The multi-phase and frequency detectors are used to compare input and feedback clocks ...
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... Phase lock detection is handled in several ways. Phase loss can be triggered from: The fine phase lock detector, which measures the phase between input and feedback clock Revision 3.01/August 2005 © Semtech Corp. FINAL The coarse phase lock detector, which monitors whole cycle slips Detection that the DPLL is at min ...
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... DPLL Feature Summary DPLL1 is the more feature rich of the two DPLLs. The features of the two DPLLs are summarized here. Refer to the Register Descriptions for more information. Revision 3.01/August 2005 © Semtech Corp. FINAL DPLL1 Main Features Multiple E1 and DS1 outputs supported ...
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... Input phase measured at DPLL1 or DPLL2. DPLL select (Reg. 4B Bit 4), 16-bit phase status (Reg. 77/Reg. 78) Phase measured between two inputs (uses DPLL2’s PFD (Reg. 65 Bit 7)) Revision 3.01/August 2005 © Semtech Corp. FINAL DPLL2 Main Features The main features of DPLL2 are: Always locked to DPLL1 ...
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... Table 7 Output Frequency Selection Frequency (MHz, unless stated otherwise) 2 kHz 2 kHz 8 kHz 8 kHz Revision 3.01/August 2005 © Semtech Corp. FINAL clocks are selectable from a range of pre-defined spot frequencies/port technologies, as defined in Tables 6 and 7. Outputs O1 & O2 Frequency Configuration Steps The output frequency selection is performed in the following steps: 6 ...
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... Digital1 or Digital2 (not Output O1) 3.088 via Digital1 or Digital2 (not Output O1) 3.728 4.096 via Digital1 or Digital2 (not Output O1) 4.096 via Digital1 or Digital2 (not Output O1) 4.296 Revision 3.01/August 2005 © Semtech Corp. FINAL DPLL1 Mode DPLL2 Mode - 12E1 mode - - - 16DS1 mode ...
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... Digital1 or Digital2 (not Output O1) 8.192 via Digital1 or Digital2 (not Output O1) 8.235 9.264 9.264 9.264 10.923 11.184 12.288 12.288 12.288 12.352 12.352 12.352 Revision 3.01/August 2005 © Semtech Corp. FINAL DPLL1 Mode DPLL2 Mode - 77.76 MHz mode - E3 mode 12E1 mode - - 12E1 mode - - 16DS1 mode ...
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... Revision 3.01/August 2005 © Semtech Corp. FINAL DPLL1 Mode DPLL2 Mode - - 77.76 MHz Analog - Any digital feedback mode - 12E1 mode - 16E1 mode - - 16E1 mode - - 77.76 MHz Analog - Any digital feedback mode ...
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... O1 only) 131.07 (Output O1 only) 148.22 (Output O1 only) 155.52 (Output O1 only) 155.52 (Output O1 only) 311.04 (Output O1 only) 311.04 (Output O1 only) Revision 3.01/August 2005 © Semtech Corp. FINAL DPLL1 Mode DPLL2 Mode - E3 mode 24DS1 mode - - 24DS1 mode - - 77.76 MHz analog - 77.76 MHz digital ...
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... Frequency DFS Frequency 311.04 MHz DPLL2-Squelched 77.76 311.04 MHz DPLL2-Normal 77.76 98.304 MHz DPLL2-12E1 24.576 131.072 MHz DPLL2-16E1 32.768 148.224 MHz DPLL2-24DS1 37.056 (2*18.528) Revision 3.01/August 2005 © Semtech Corp. FINAL APLL/2 APLL/4 APLL/6 APLL/8 155.52 77.76 51.84 38.88 137.472 68.376 - 34.368 89.472 44.736 - 22.368 74.112 37 ...
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... Revision 3.01/August 2005 © Semtech Corp. FINAL DPLL2 Freq Control APLL2 Input from Register Bits DPLL1 or 2. (MHz) Reg. 64 Bits [2:0] Reg. 65 Bit 6 101 0 (DPLL2 enabled) 110 0 (DPLL2 enabled) ...
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... Clock non-inverted, Reg.7A[3: Output FrSync at 8 kHz, or Output 01 at 8kHz b) Pulse non-inverted, Reg.7A[3: Revision 3.01/August 2005 © Semtech Corp. FINAL 8 kHz options available from the O1 and O2 outputs are all supplied via DPLL1 or DPLL2 (Reg. 7A Bit 7). The outputs can be either clocks (50:50 mark-space) or pulses, and can be inverted ...
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... GR-1244-CORE specification, if the selected SEC is of good quality. If the device cannot achieve lock within 100 seconds, it reverts to Free-Run mode and another SEC is selected. Revision 3.01/August 2005 © Semtech Corp. FINAL Locked Mode The Locked mode is entered from Pre-locked, Pre-locked2 or Phase-lost mode when an input reference source has been selected and the DPLL has locked ...
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... DPLL1_operating _mode. By contrast, the DPLL2 has only automatic operation and can be in one of only two possible states: “Instantaneous Automatic Holdover” with zero frequency offset (its start-up state), or “Locked”. The states of DPLL2 are not configurable by the User and there is no “Free-run” state. Revision 3.01/August 2005 © Semtech Corp. FINAL Free-run ...
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... These effects must be limited by careful selection of a suitable component for the local oscillator. Please contact Semtech for information on crystal oscillator suppliers. Crystal Frequency Calibration The absolute crystal frequency accuracy is less important than the stability since any frequency offset can be compensated by adjustment of register values in the IC ...
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... Enabling this phase measurement feature replaces the DPLL2 feedback signal to the DPLL2 PFD Revision 3.01/August 2005 © Semtech Corp. FINAL with the DPLL1 PFD input reference signal. Reading the current phase register from DPLL2 will yield the filtered phase difference between the two inputs ...
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... Bit 7 and Reg. 09, Bit 7). The check for consistent phase involves checking that each input edge is within an expected timing window. The Revision 3.01/August 2005 © Semtech Corp. FINAL Sync Input Sync Input ...
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... DPLL1. 2 kHz and 8 kHz outputs can also be produced at the outputs. These can come from either the DPLL1 or from the DPLL2, controlled by Reg. 7A, Bit 7. Revision 3.01/August 2005 © Semtech Corp. FINAL Power-On Reset The Power-On Reset (PORB) pin resets the device if forced Low ...
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... SCLK High time pw2 t Hold SDI valid after SCLK h1 t Hold CSB Low after SCLK h2 Hold CSB Low after SCLK t Time between consecutive accesses (CSB p Revision 3.01/August 2005 © Semtech Corp. FINAL t pw2 pw1 ...
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... SCLK High time pw2 t Hold SDI valid after SCLK h1 t Hold CSB Low after SCLK h2 t Time between consecutive accesses (CSB p Revision 3.01/August 2005 © Semtech Corp. FINAL t pw2 pw1 Parameter rising edge rising edge rising edge ...
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... All status registers may be read at any time and, in some status registers (such as the sts_interrupts register), any individual data field may be Revision 3.01/August 2005 © Semtech Corp. FINAL cleared by writing a 1 into each bit of the field (writing a 0 value into a bit will not affect the value of the bit). ...
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... A0 cnfg_differential_inputs (R/ cnfg_dig_outputs_sonsdh (R/ cnfg_digtial_frequencies (R/ cnfg_differential_output (R/ cnfg_auto_bw_sel 3B 98 auto_BW_sel cnfg_nominal_frequency [7: (R/W) [15: cnfg_DPLL_freq_limit (R/W) [7: Revision 3.01/August 2005 © Semtech Corp. FINAL chip_id[7:0], 8 LSBs of Chip ID chip_id[15:8], 8 MSBs of Chip ID chip_revision[7:0] Disable_180 Resync_ analog status_SEC2_ status_SEC1_ DIFF DIFF DPLL1_main_ ref_failed ...
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... C2 DPLL2_PD2_ gain_enable cnfg_DPLL1_PD2_gain (R/ DPLL1_PD2_ gain_enable cnfg_phase_offset (R/W) [7: [15: cnfg_PBO_phase_offset (R/ cnfg_phase_loss_fine_limit (R/ fine_limit_en Revision 3.01/August 2005 © Semtech Corp. FINAL Data Bit Set to 0 SEC2 DIFF SEC1 DIFF SEC2 TTL main_ref_ failed divn_value [7:0] (divide Input frequency by n) ...
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... DPLL2 cnfg_sync_phase (R/ Indep_FrSync/ MFrSync cnfg_sync_monitor (R/ ph_offset_ ramp cnfg_interrupt (R/ cnfg_protection(R/ Revision 3.01/August 2005 © Semtech Corp. FINAL Data Bit wide_range_ multi_ph_resp en current_phase[7:0] current_phase[15:8] timeout_value (in two-second intervals) 8k_invert Sync_OC-N_ Sync_phase_SYNC3 rates Sync_monitor_limit protection_value ...
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... Most significant byte of the 2-byte device ID. 02 Address (hex): Register Name chip_revision Bit 7 Bit 6 Bit No. Description [7:0] chip_revision Silicon revision of the device. Revision 3.01/August 2005 © Semtech Corp. FINAL Description (RO) 8 least significant bits of the chip ID. Bit 5 Bit 4 Bit 3 chip_id[7:0], 8 LSBs of Chip ID Bit Value 48 (hex) Description (RO) 8 most significant bits of the chip ID ...
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... Set to 0 Test Control. Leave unchanged or set Set to 0 Test Control. Leave unchanged or set Address (hex): test_register2 Revision 3.01/August 2005 © Semtech Corp. FINAL Description (R/W) Register containing various test controls (not normally used). Bit 5 Bit 4 Bit 3 resync_analog Set to 0 ...
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... DPLL1_ mode main_ref_failed Bit No. Description 7 operating_mode Interrupt indicating that the operating mode has changed. Latched until reset by software writing this bit. Revision 3.01/August 2005 © Semtech Corp. FINAL Description (R/W) Bits [7:0] of the interrupt status register. Bit 5 Bit 4 Bit 3 status_SEC1_ status_SEC2_ DIFF ...
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... Not used. [2:0] Bits [18:16] of sts_current_DPLL_frequency When Bit 4 (DPLL1_DPLL2_select) of Reg. 4B (cnfg_registers_source_select the frequency for DPLL1 is reported. When this Bit the frequency for DPLL2 is reported. Revision 3.01/August 2005 © Semtech Corp. FINAL Description (R/W) Bits [15:8] of the interrupt status register. Bit 5 Bit 4 Bit 3 Bit Value ...
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... Bit 7 Bit 6 Sync_alarm DPLL2_Lock DPLL1_freq_ soft_alarm Bit No. Description 7 Sync_alarm Reports current interrupt status of the selected Sync input monitor. Revision 3.01/August 2005 © Semtech Corp. FINAL Description (R/W) Bits [23:16] of the interrupt status register. Bit 5 Bit 4 Bit 3 Bit Value Description (RO) Current operating state of the device’ ...
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... DPLL2 locked bit, in order to get a current indication of whether the DPLL2 is locked. Revision 3.01/August 2005 © Semtech Corp. FINAL Description (RO) Current operating state of the device’s internal state machine ...
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... Not used. [2:0] DPLL1_operating_mode This field is used to report the state of the internal finite state machine controlling DPLL1. Revision 3.01/August 2005 © Semtech Corp. FINAL Description (RO) Current operating state of the device’s internal state machine. Bit 5 ...
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... Currently selected source Reports the input channel number of the currently selected source. When in Non-revertive mode, this is not necessarily the same as the highest priority validated source. Revision 3.01/August 2005 © Semtech Corp. FINAL Description (RO) Bits [7:0] of the validated priority table. Bit 5 Bit 4 ...
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... Reports the input channel number of the 3 priority validated source. nd [3:0] 2 highest priority validated Reports the input channel number of the 2 highest priority validated source. Revision 3.01/August 2005 © Semtech Corp. FINAL Description (RO) Bits [15:8] of the validated priority table. Bit 5 Bit 4 Bit 3 Bit Value ...
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... Reg. 0C and Reg represent the current frequency offset of the DPLL. *When Bit 4 (DPLL1_DPLL2_select) of Reg. 4B (cnfg_registers_source_select the frequency for DPLL1 is reported. When this Bit the frequency for DPLL2 is reported. Revision 3.01/August 2005 © Semtech Corp. FINAL Description (RO) Bits [7:0] of the current DPLL frequency. Bit 5 Bit 4 ...
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... Bit 7 Bit 6 Bit No. Description [7:1] Not used. 0 SEC3 Bit indicating if SEC3 is valid. The input is valid if it has no outstanding alarms. Revision 3.01/August 2005 © Semtech Corp. FINAL Description (RO) 8 least significant bits of the sts_sources_valid register. Bit 5 Bit 4 Bit 3 SEC1 DIFF SEC2 TTL Bit Value ...
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... SEC2 TTL. The smaller the number, the higher the priority; zero disables the input. *When the priority of this input is set to >0, the priority of SEC2 DIFF is set to 0 (disabled). Revision 3.01/August 2005 © Semtech Corp. FINAL Description (RO except for test when R/W) Reports any alarms active on inputs ...
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... SEC1 DIFF. The smaller the number, the higher the priority; zero disables the input. *When the priority of this input is set to >0, the priority of SEC1 TTL is set to 0 (disabled). Revision 3.01/August 2005 © Semtech Corp. FINAL Description (R/W) Configures the relative priority of input sources SEC1 TTL and SEC2 TTL ...
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... Every input has its own Leaky Bucket used for activity monitoring. There are four possible configurations for each Leaky Bucket- see Reg Reg. 5F. This 2-bit field selects the configuration used for input <input>. Revision 3.01/August 2005 © Semtech Corp. FINAL Description (R/W) Configures the relative priority of input source SEC3. ...
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... Use description for Reg. 22, but use <input> = SEC3 32 Address (hex): Register Name cnfg_operating_mode Bit 7 Bit 6 Bit No. Description [7:3] Not used. Revision 3.01/August 2005 © Semtech Corp. FINAL Description (R/W) Configuration of the frequency and input monitoring for input <input>. Bit 5 Bit 4 Bit 3 Bucket_id_<input> Bit Value ...
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... To ensure selection of the programmed input reference under all circumstances, revertive mode should be enabled (Reg. 34 bit 0 set to “1”). Revision 3.01/August 2005 © Semtech Corp. FINAL Description (R/W) Register to force the state of DPLL1 controlling state machine ...
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... Non-revertive mode, the device will not automatically switch to a higher priority source, unless the current source fails. When in Revertive mode the device will always select the highest priority source. Revision 3.01/August 2005 © Semtech Corp. FINAL Description (R/W) Register controlling various input modes of the device. ...
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... Configures the SEC2 DIFF input to be compatible with either 3 V LVDS PECL electrical levels. 0 SEC1_DIFF_PECL Configures the SEC1 DIFF input to be compatible with either 3 V LVDS PECL electrical levels. Revision 3.01/August 2005 © Semtech Corp. FINAL Description (R/W) Register to configure the feedback mode of DPLL2. Bit 5 ...
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... SONET or SDH based is configured by Bit 6 (dig2_sonsdh) of Reg. 38. [5:4] digital1_frequency Configures the frequency of Digital1. Whether this is SONET or SDH based is configured by Bit 5 (dig1_sonsdh) of Reg. 38. [3:0] Not used. Revision 3.01/August 2005 © Semtech Corp. FINAL Description Configures Digital1 and Digital2 output frequencies to be SONET or SDH compatible frequencies. Bit 5 Bit 4 Bit 3 ...
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... DPLL is pulling in. Note that when this happens, the reported frequency value, via current_DPLL_freq (Reg. 0C, 0D and 07) is also frozen. [2:0] Not used. Revision 3.01/August 2005 © Semtech Corp. FINAL Description (R/W) Configures the electrical compatibility of the differential output driver PECL LVDS ...
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... This means that the value programmed will affect the value reported in the sts_current_DPLL_frequency (Reg. 07/0D/0C). IIt will also affect the value programmed into the DPLL frequency offset limit . Revision 3.01/August 2005 © Semtech Corp. FINAL Description (R/W) Bits [7:0] of the register used to calibrate the crystal oscillator used to clock the device ...
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... Address (hex): Register Name cnfg_DPLL_freq_limit [9:8] Bit 7 Bit 6 Bit No. Description [7:2] Not used. [1:0] Bits [9:8] of cnfg_DPLL_freq_limit. Revision 3.01/August 2005 © Semtech Corp. FINAL Description (R/W) Bits [7:0] of the DPLL frequency limit register. Bit 5 Bit 4 Bit 3 Bits[7:0] of cnfg_DPLL_freq_limit Bit Value - Description (R/W) Bits [9:8] of the DPLL frequency limit register. ...
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... Mask bit for main_ref_failed interrupt. [5:3] Not used. 2 Set Not used. 0 SEC3 Mask bit for input SEC3 interrupt. Revision 3.01/August 2005 © Semtech Corp. FINAL Description (R/W) Bits [7:0] of the interrupt mask register. Bit 5 Bit 4 Bit 3 SEC1 DIFF SEC2 TTL Bit Value ...
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... Description [7:0] divn_value[7:0]. 47 Address (hex): Register Name cnfg_freq_divn [13:8] Bit 7 Bit 6 Bit No. Description [7:6] Not used. Revision 3.01/August 2005 © Semtech Corp. FINAL Description (R/W) Bits [23:16] of the interrupt mask register. Bit 5 Bit 4 Bit 3 Bit Value Description (R/W) Bits [7:0] of the division factor for inputs using the DivN feature ...
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... Bit to enable ultra-fast switching mode. When in this mode, the device will disqualify a locked-to source as soon as it detects a few missing input cycles. Revision 3.01/August 2005 © Semtech Corp. FINAL Description (R/W) Bits [13:8] of the division factor for inputs using the DivN feature. ...
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... Bit to enable Phase Build-out events on source switching. When enabled a Phase Build-out event is triggered every time DPLL1 selects a new source- this includes exiting the Holdover or Free-run states. 1 Not used. Revision 3.01/August 2005 © Semtech Corp. FINAL Description (R/W) Configuration register controlling several input monitoring and switching options. ...
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... Reg. 41 and Reg. 42 (cnfg_DPLL_freq_limit). This results in the DPLL entering the phase lost state any time the DPLL tracks to the extent of its hard limit. [6:0] Not used. Revision 3.01/August 2005 © Semtech Corp. FINAL Description (R/W) Register to select the source of many of the registers. Bit 5 ...
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... Reg. 53 (cnfg_decay_rate_0), in which this does not occur, the accumulator is decremented by 1. The lower_threshold_0_value is the value at which the Leaky Bucket will reset an inactivity alarm. Revision 3.01/August 2005 © Semtech Corp. FINAL Description (R/W) Register to program the activity alarm setting limit for Leaky Bucket Configuration 0. ...
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... The Leaky Bucket can be programmed to “leak” or “decay” at the same rate as the “fill” cycle, or effectively at one half, one quarter, or one eighth of the fill rate. Revision 3.01/August 2005 © Semtech Corp. FINAL Description (R/W) Register to program the maximum size limit for Leaky Bucket Configuration 0 ...
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... Reg. 57 (cnfg_decay_rate_1), in which this does not occur, the accumulator is decremented by 1. The lower_threshold_1_value is the value at which the Leaky Bucket will reset an inactivity alarm. Revision 3.01/August 2005 © Semtech Corp. FINAL Description (R/W) Register to program the activity alarm setting limit for Leaky Bucket Configuration 1. ...
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... The Leaky Bucket can be programmed to “leak” or “decay” at the same rate as the “fill” cycle, or effectively at one half, one quarter, or one eighth of the fill rate. Revision 3.01/August 2005 © Semtech Corp. FINAL Description (R/W) Register to program the maximum size limit for Leaky Bucket Configuration 1 ...
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... Reg. 5B (cnfg_decay_rate_2), in which this does not occur, the accumulator is decremented by 1. The lower_threshold_2_value is the value at which the Leaky Bucket will reset an inactivity alarm. Revision 3.01/August 2005 © Semtech Corp. FINAL Description (R/W) Register to program the activity alarm setting limit for Leaky Bucket Configuration 2. ...
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... The Leaky Bucket can be programmed to “leak” or “decay” at the same rate as the “fill” cycle, or effectively at one half, one quarter, or one eighth of the fill rate. Revision 3.01/August 2005 © Semtech Corp. FINAL Description (R/W) Register to program the maximum size limit for Leaky Bucket Configuration 2 ...
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... Reg. 5F (cnfg_decay_rate_3), in which this does not occur, the accumulator is decremented by 1. The lower_threshold_3_value is the value at which the Leaky Bucket will reset an inactivity alarm. Revision 3.01/August 2005 © Semtech Corp. FINAL Description (R/W) Register to program the activity alarm setting limit for Leaky Bucket Configuration 3. ...
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... The Leaky Bucket can be programmed to “leak” or “decay” at the same rate as the “fill” cycle, or effectively at one half, one quarter, or one eighth of the fill rate. Revision 3.01/August 2005 © Semtech Corp. FINAL Description (R/W) Register to program the maximum size limit for Leaky Bucket Configuration 3 ...
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... Output O2. Many of the frequencies available are dependent on the frequencies of the APLL1 and the APLL2. These are configured in Reg. 64 and Reg. 65. For more detail see the detailed section on configuring the output frequencies. Revision 3.01/August 2005 © Semtech Corp. FINAL Description (R/W) Register to configure and enable the frequencies available on Output O2 ...
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... MFrSync_en Register bit to enable the 2 kHz Sync output (MFrSync). 6 FrSync_en Register bit to enable the 8 kHz Sync output (FrSync). [5:0] Not used. Revision 3.01/August 2005 © Semtech Corp. FINAL Description (R/W) Register to configure and enable the frequencies available on Output O1. Bit 5 Bit 4 Bit 3 Bit Value ...
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... Between Master and Slave/Stand-by SEC Sources” on page 33. 6 APLL2_for_DPLL1_E1/DS1 Register bit to select whether the APLL2 takes its input from DPLL2 or DPLL1. If DPLL1 is selected then the frequency is controlled by Bits [5:4], DPLL1_freq_to_APLL2. Revision 3.01/August 2005 © Semtech Corp. FINAL Description (R/W) Register to configure DPLL2 Frequency. Bit 5 Bit 4 Bit 3 ...
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... Output DFS block. See Figure 5 “PLL Block Diagram” on page 15. Note...001 is the only selection that does not bypass APLL3. All other selections use digital feedback. Revision 3.01/August 2005 © Semtech Corp. FINAL Description (R/W) Register to configure DPLL1 and several other parameters. ...
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... Address (hex): Register Name cnfg_DPLL1_acq_bw Bit 7 Bit 6 Bit No. Description [7:4] Not used. Revision 3.01/August 2005 © Semtech Corp. FINAL Description (R/W) Register to configure the bandwidth of DPLL2. Bit 5 Bit 4 Bit 3 Bit Value - ...
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... This setting is only used if automatic gain selection is enabled in Reg. 6C Bit 7, cnfg_DPLL2_PD2_gain. 3 Not used. Revision 3.01/August 2005 © Semtech Corp. FINAL Description (R/W) Register to configure the bandwidth of DPLL1, when not phase locked to an input. ...
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... This setting is only used if automatic gain selection is enabled in Reg. 6D Bit 7, cnfg_DPLL1_PD2_gain. 3 Not used. Revision 3.01/August 2005 © Semtech Corp. FINAL Description (R/W) Register to configure the damping factor of DPLL2, along with the gain of Phase Detector 2 in some modes ...
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... This setting is not used if automatic gain selection is disabled in Bit 7, DPLL2_PD2_gain_enable. 3 Not used. Revision 3.01/August 2005 © Semtech Corp. FINAL Description (R/W) Register to configure the damping factor of DPLL1, along with the gain of the Phase Detector 2 in some modes ...
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... This setting is not used if automatic gain selection is disabled in Bit 7, DPLL1_PD2_gain_enable. 3 Not used. Revision 3.01/August 2005 © Semtech Corp. FINAL Description (R/W) Register to configure the gain of Phase Detector 2 in some modes for DPLL2. ...
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... Address (hex): Register Name cnfg_phase_offset [7:0] Bit 7 Bit 6 Bit No. Description [7:0] phase_offset_value[7:0] Register forming part of the phase offset control. Revision 3.01/August 2005 © Semtech Corp. FINAL Description (R/W) Register to configure the gain of Phase Detector 2 in some modes for DPLL1. Bit 5 Bit 4 Bit 3 Bit Value - ...
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... Phase Build-out is enabled in either Reg Reg. 76. 72 Address (hex): Register Name cnfg_PBO_phase_offset Bit 7 Bit 6 Bit No. Description [7:6] Not used. Revision 3.01/August 2005 © Semtech Corp. FINAL Description (R/W) Bits [15:8] of the phase offset control register. Bit 5 Bit 4 Bit 3 phase_offset_value[15:8] Bit Value - Description (R/W) Register to offset the mean time error of Phase Build-out events ...
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... If phase loss is indicated, then frequency and phase locking is instigated (±360º locking). This bit can be used to force the DPLL to indicate phase loss immediately when no activity is detected. Revision 3.01/August 2005 © Semtech Corp. FINAL Description (R/W) Register to offset the mean time error of Phase Build-out events ...
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... Bits [3:0]. This register sets the limit in the number of input clock cycles (UI) that the input phase can move by before the DPLL indicates phase lost. Revision 3.01/August 2005 © Semtech Corp. FINAL Description (R/W) Register to configure some of the parameters of the DPLL phase detectors ...
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... MHz input, would give the same dynamic response as a 19.44 MHz input used with 8 k locking mode, where the input is divided down internally to 8 kHz first. 4 Not used. Revision 3.01/August 2005 © Semtech Corp. FINAL Description (R/W) Register to configure some of the parameters of DPLL phase detectors. ...
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... DPLL. This reduces any possible phase hit when a low-frequency connection is removed and contact bounce is possible. [6:0] Not used. Revision 3.01/August 2005 © Semtech Corp. FINAL Description (R/W) Register to configure some of the parameters of DPLL phase detectors. Bit 5 ...
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... Address (hex): Register Name cnfg_phase_alarm_timeout Bit 7 Bit 6 Bit No. Description [7:6] Not used. Revision 3.01/August 2005 © Semtech Corp. FINAL Description (RO) Bits [7:0] of the current phase register. Bit 5 Bit 4 Bit 3 current_phase[7:0] Bit Value - Description (RO) Bits [15:8] of the current phase register ...
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... FrSync output, and then the pulse width on the FrSync output will be equal to the period of the output programmed on O2. Revision 3.01/August 2005 © Semtech Corp. FINAL Description (R/W) Register to configure how long before a phase alarm is raised on an input ...
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... FrSync and other clock outputs during synchronisation from the selected Sync input, or whether to not maintain alignment to all clocks and so not disturb any of the output clocks. Revision 3.01/August 2005 © Semtech Corp. FINAL Description (R/W) Register to configure the Sync outputs available from ...
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... Register to control the sampling of the external Sync input. Nominally the falling edge of the input is aligned with the falling edge of the reference clock. The margin is ±0.5 U.I. (Unit Interval). Revision 3.01/August 2005 © Semtech Corp. FINAL Description (R/W) Register to configure the behaviour of the synchronisation for the external frame reference ...
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... Address (hex): Register Name cnfg_interrupt Bit 7 Bit 6 Bit No. Description [7:3] Not used. Revision 3.01/August 2005 © Semtech Corp. FINAL Description (R/W) Register to configure the external Sync input monitor. It also has a bit to control the phase offset automatic ramping feature. Bit 5 Bit 4 Bit 3 Bit Value ...
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... When fully unprotected, any writeable register in the device can be written to. When single unprotected, only one register can be written before the device automatically re-protects itself. Note...This register cannot be protected. Revision 3.01/August 2005 © Semtech Corp. FINAL Description (R/W) Register to configure interrupt output. ...
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... Table 16 JTAG Timing (for use with Figure 12) Parameter Cycle Time TMS/TDI to TCK rising edge time TCK rising to TMS/TDI hold time TCK falling to TDO valid Revision 3.01/August 2005 © Semtech Corp. FINAL Over-voltage Protection The ACS8525 may require Over-voltage Protection on input reference clock ports according to ITU recommendation K.41 are recommended for this purpose (see separate Semtech data book) ...
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... Supply Current (Typical - one 19 MHz output) Total Power Dissipation DC Characteristics Table 19 DC Characteristics: TTL Input Port Across all operating conditions, unless otherwise stated Parameter V High IN V Low IN Input Current Revision 3.01/August 2005 © Semtech Corp. FINAL Symbol Minimum V -0 DD5V ...
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... Table 23 DC Characteristics: PECL Input/Output Port Across all operating conditions, unless otherwise stated Parameter PECL Input Low Voltage Differential Inputs (Note ii) PECL Input High Voltage Differential Inputs (Note ii) Input Differential Voltage Revision 3.01/August 2005 © Semtech Corp. FINAL Symbol Minimum Typical ...
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... MHz, 38.88 MHz 50Ω 51.84 MHz, O 77.76 MHz or 155.52 MHz kHz 50Ω 1.544/2.048 MHz, O 6.48 MHz, 19.44 MHz, 38.88 MHz 50Ω 51.84 MHz, O 77.76 MHz or 155.52 MHz Revision 3.01/August 2005 © Semtech Corp. FINAL Symbol Minimum V V -2.4 ILPECL_S -1.3 ILPECL_S DD I -10 IHPECL I -10 ILPECL ...
Page 102
... MHz 50Ω 51.84 MHz, O 77.76 MHz or 155.52 MHz kHz, 1.544/2.048 MHz 50Ω O 6.48 MHz, 19.44 MHz, 38.88 MHz, 51.84 MHz 50Ω O 77.76 MHz or 155.52 MHz Revision 3.01/August 2005 © Semtech Corp. FINAL Symbol Minimum V 0 VRLVDS V -100 DITH V 0.1 IDLVTSDS R 95 TERM V - OHLVDS V 0.885 ...
Page 103
... MHz [6] G-742 for 2.048 MHz [6] G-742 for 2.048 MHz [5] G-736 for 2.048 MHz Revision 3.01/August 2005 © Semtech Corp. FINAL Test Definition Filter 65 kHz - 1.3 MHz 100 kHz 12 kHz - 1.3 MHz kHz 500 Hz - 1.3 MHz 65 kHz - 1.3 MHz 100 kHz ...
Page 104
... MHz Note...This table is only for comparing the ACS8525 output jitter performance against values and quoted in various specifications for given conditions. It should not be used to infer compliance to any other aspects of these specifications. Revision 3.01/August 2005 © Semtech Corp. FINAL Test Definition ...
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... MHz input 25.92 MHz output 38.88 MHz input 38.88 MHz output 51.84 MHz input 51.84 MHz output 77.76 MHz input 77.76 MHz output 155.52 MHz input 155.52 MHz output Revision 3.01/August 2005 © Semtech Corp. FINAL Delay Output MFrSync (2 kHz) +8.2 ± 1.5 ns FrSync (8 kHz) +4.7 ± 1 kHz 2 kHz +4.3 ± 1.5 ns DS1 (1.544 MHz) +4.7 ± ...
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... These dimensions apply to the flat section of the lead between 0.10 mm and 0.25 mm from the lead tip. 8 Shows plating. Table 26 64 Pin LQFP Package Dimension Data (for use with Figure 16) Dimensions D/E D1 Min 1.40 0.05 1.35 Nom. 12.00 10.00 1.50 0.10 1.40 0.50 12 Max 1.60 0.15 1.45 Revision 3.01/August 2005 © Semtech Corp. FINAL AN1 AN2 AN3 AN4 ...
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... Figure 17 Typical 64-Pin LQFP Package Landing Pattern Pitch 0 0.5 mm Notes: (i) Solderable to this limit. (ii) Square package - dimensions apply in both X and Y directions. (iii) Typical example. The user is responsible for ensuring compatibility with PCB manufacturing process, etc. Revision 3.01/August 2005 © Semtech Corp. FINAL 1.85 1.85 mm Widt idth h 0 F8525D_029LQFootprt64 ...
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... ZD1 BZV90C-5.6v VDD C-MAC E2747_ 12.8MHz C17 10 GND VDDA GNDb 4 100nF DGND X1 DGND DGND2 Revision 3.01/August 2005 © Semtech Corp. FINAL VDD3 VDD VDD2 IC2 3 2 VIN VOUT 1 GND VDDA EZ1086CM-3 100nF 10uF_TANT AGND DGND2 DGND ...
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... Temperature Compensated Crystal Oscillator UI Unit Interval WEEE Waste Electrical and Electronic Equipment (directive) XO Crystal Oscillator Revision 3.01/August 2005 © Semtech Corp. FINAL References [1] AT & T 62411 (12/1990) ® ACCUNET T1.5 Service description and Interface Specification [2] ETSI ETS 300 462-3, (01/1997) Transmission and Multiplexing (TM); Generic requirements for synchronization networks ...
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... ADVANCED COMMUNICATIONS Trademark Acknowledgements Semtech and the Semtech S logo are registered trademarks of Semtech Corporation. ACCUNET ® registered trademark of AT & T. C-MAC is a registered trademark of C-MAC MicroTechnology - a division of Solectron Corporation. ICT Flexacom is a registered trademark of ICT Electronics. Motorola is a registered trademark of Motorola, Inc. ...
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... Phrase in first line, first para: “(including Auto-PBO on phase transients)” removed. Register descriptions (and register map where appropriate) updated. Reference to “Semtech Corp.”as a registered trademark now removed. Paragraph changed. Abbreviation “pk-pk” changed to “p-p” throughout. Header bar updated (for Internation AG variant only) stating “ADVANCED COMMUNICATIONS” ...
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... Ordering Information Table 28 Parts List Part Number ACS8525 ACS8525T Disclaimers Life support- This product is not designed or intended for use in life support equipment, devices or systems, or other critical applications. This product is not authorized or warranted by Semtech for such use. Right to change- Semtech Corporation reserves the right to make changes, without notice, to this product. Customers are advised to obtain the latest version of the relevant information before placing orders. Compliance to relevant standards- Operation of this device is subject to the User’ ...