IC ASYNCH BINARY COUNTER 16-SOIC

 

SN74LV4040ADRG4

Manufacturer Part NumberSN74LV4040ADRG4
DescriptionIC ASYNCH BINARY COUNTER 16-SOIC
ManufacturerTexas Instruments
Series74LV
SN74LV4040ADRG4 datasheets

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Specifications of SN74LV4040ADRG4

Logic TypeBinary CounterDirectionUp
Number Of Elements1Number Of Bits Per Element12
ResetAsynchronousTimingAsynchronous
Count Rate95MHzTrigger TypeNegative Edge
Voltage - Supply2 V ~ 5.5 VOperating Temperature-40°C ~ 85°C
Mounting TypeSurface MountPackage / Case16-SOIC (3.9mm Width)
Lead Free Status / RoHS StatusLead free / RoHS Compliant  
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PARAMETER MEASUREMENT INFORMATION
From Output
Test
From Output
Under Test
Point
C L
(see Note A)
LOAD CIRCUIT FOR
TOTEM-POLE OUTPUTS
t w
50% V CC
Input
VOLTAGE WAVEFORMS
PULSE DURATION
50% V CC
50% V CC
Input
t PLH
In-Phase
50% V CC
Output
t PHL
Out-of-Phase
50% V CC
Output
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
NOTES: A. C L includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, Z O = 50 Ω, t r ≤ 3 ns, t f ≤ 3 ns.
D. The outputs are measured one at a time, with one input transition per measurement.
E. All parameters and waveforms are not applicable to all devices.
Figure 1. Load Circuit and Voltage Waveforms
V CC
S1
R L = 1 kΩ
GND
Under Test
C L
(see Note A)
LOAD CIRCUIT FOR
3-STATE AND OPEN-DRAIN OUTPUTS
Timing Input
V CC
50% V CC
Data Input
0 V
V CC
Output
Control
0 V
t PZL
t PHL
Output
V OH
Waveform 1
50% V CC
S1 at V CC
V OL
(see Note B)
t PLH
t PZH
Output
V OH
Waveform 2
50% V CC
S1 at GND
V OL
(see Note B)
LOW- AND HIGH-LEVEL ENABLING
•
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
SCES226I − APRIL 1999 − REVISED MAY 2005
Open
TEST
S1
t PLH /t PHL
Open
t PLZ /t PZL
V CC
t PHZ /t PZH
GND
Open Drain
V CC
V CC
50% V CC
0 V
t h
t su
V CC
50% V CC
50% V CC
0 V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
V CC
50% V CC
50% V CC
0 V
t PLZ
≈V CC
50% V CC
V OL + 0.3 V
V OL
t PHZ
V OH
V OH − 0.3 V
50% V CC
≈0 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
7

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