IDT71V424S Integrated Device Technology, IDT71V424S Datasheet
IDT71V424S
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IDT71V424S Summary of contents
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... Fully static asynchronous circuitry is used, requiring no clocks or refresh for operation. The IDT71V424 is packaged in a 36-pin, 400 mil Plastic SOJ and 44- pin, 400 mil TSOP. • • • • ADDRESS • DECODER • CONTROL LOGIC 1 IDT71V424S IDT71V424L 4,194,304-BIT MEMORY ARRAY 8 I/O CONTROL 3622 drw 01 JULY 2004 DSC-3622/06 ...
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... IDT71V424S, IDT71V424L, 3.3V CMOS Static RAM 4 Meg (512K x 8-bit) Pin Configuration I I SO36 I I SOJ Top View Pin Description A – A Address Inputs Chip Select ...
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... IDT71V424S, IDT71V424L, 3.3V CMOS Static RAM 4 Meg (512K x 8-bit) Absolute Maximum Ratings Symbol Rating V Supply Voltage Relative Terminal Voltage Relative IN OUT Temperature Under Bias BIAS T Storage Temperature STG P Power Dissipation Output Current OUT NOTE: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device ...
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... IDT71V424S, IDT71V424L, 3.3V CMOS Static RAM 4 Meg (512K x 8-bit) AC Test Conditions Input Pulse Levels Input Rise/Fall Times Input Timing Reference Levels Output Reference Levels AC Test Load AC Test Loads +1.5V I 50Ω 0 Figure 1. AC Test Load 7 6 ∆t t AA, ACS 5 (Typical, ns • ...
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... IDT71V424S, IDT71V424L, 3.3V CMOS Static RAM 4 Meg (512K x 8-bit) AC Electrical Characteristics (V = 3.3V ± 10%, Commercial and Industrial Temperature Ranges) CC Symbol READ CYCLE t Read Cycle Time RC t Address Access Time AA t Chip Select Access Time ACS (1) Chip Select to Output in Low-Z t CLZ (1) Chip Deselect to Output in High-Z ...
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... IDT71V424S, IDT71V424L, 3.3V CMOS Static RAM 4 Meg (512K x 8-bit) Timing Waveform of Read Cycle No. 1 ADDRESS OE CS DATA OUT SUPPLY CC CURRENT I SB Timing Waveform of Read Cycle No. 2 ADDRESS PREVIOUS DATA DATA OUT NOTES HIGH for Read Cycle. 2. Device is continuously selected LOW. ...
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... IDT71V424S, IDT71V424L, 3.3V CMOS Static RAM 4 Meg (512K x 8-bit) Timing Waveform of Write Cycle No. 1 (WE Controlled Timing) ADDRESS DATA OUT DATA IN Timing Waveform of Write Cycle No. 2 (CS Controlled Timing) ADDRESS DATA IN NOTES write occurs during the overlap of a LOW CS and a LOW WE. ...
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... IDT71V424S, IDT71V424L, 3.3V CMOS Static RAM 4 Meg (512K x 8-bit) Ordering Information IDT X 71V424 X Die Device Power Type Revision XX XXX X X Speed Package Process/ Temperature Range Blank 10 Blank * Commercial only for low power 10ns (L10) speed grade. 6.42 8 Commercial and Industrial Temperature Ranges Commercial (0° ...
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... IDT71V424S, IDT71V424L, 3.3V CMOS Static RAM 4 Meg (512K x 8-bit) Datasheet Document History 8/13/99 Updated to new format Pg. 2 Removed SO44-1 from TSOP pinout Pg. 7 Revised footnotes on Write Cycle No. 1 diagram Removed footnote for t Pg. 9 Added Datasheet Document History 8/31/99 Pg. 1–9 Added Industrial temperature range offerings 11/22/02 Pg ...