IDT71V124SA Integrated Device Technology, IDT71V124SA Datasheet

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IDT71V124SA

Manufacturer Part Number
IDT71V124SA
Description
3.3v Cmos Static Ram 1 Meg 128k X 8-bit Center Power & Ground Pinout
Manufacturer
Integrated Device Technology
Datasheet

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Functional Block Diagram
©2007- Integrated Device Technology, Inc.
128K x 8 advanced high-speed CMOS static RAM
JEDEC revolutionary pinout (center power/GND) for
reduced noise
Equal access and cycle times
– Commercial: 10/12/15/20ns
– Industrial: 10/12/15/20ns
One Chip Select plus one Output Enable pin
Inputs and outputs are LVTTL-compatible
Single 3.3V supply
Low power consumption via chip deselect
Available in a 32-pin 300- and 400-mil Plastic SOJ, and
32-pin Type II TSOP packages.
I/O
0
- I/O
A
A
16
7
0
WE
OE
CS
8
ADDRESS
DECODER
8
3.3V CMOS Static RAM
1 Meg (128K x 8-Bit)
Center Power &
Ground Pinout
CONTROL
LOGIC
1
Description
as 128K x 8. It is fabricated using IDT’s high-performance, high-reliability
CMOS technology. This state-of-the-art technology, combined with inno-
vative circuit design techniques, provides a cost-effective solution for high-
speed memory needs. The JEDEC center power/GND pinout reduces
noise generation and improves system performance.
5ns, with address access times as fast as 9ns available. All bidirec-
tional inputs and outputs of the IDT71V124 are LVTTL-compatible and
operation is from a single 3.3V supply. Fully static asynchronous
circuitry is used; no clocks or refreshes are required for operation.
The IDT71V124 is a 1,048,576-bit high-speed static RAM organized
The IDT71V124 has an output enable pin which operates as fast as
MEMORY ARRAY
I/O CONTROL
1,048,576-BIT
IDT71V124SA/HSA
3873 drw 01
FEBRUARY 2007
8
.
DSC-3873/09

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IDT71V124SA Summary of contents

Page 1

... IDT71V124 are LVTTL-compatible and operation is from a single 3.3V supply. Fully static asynchronous circuitry is used; no clocks or refreshes are required for operation. • • ADDRESS MEMORY ARRAY • DECODER 8 CONTROL LOGIC 1 IDT71V124SA/HSA 1,048,576-BIT 8 I/O CONTROL . 3873 drw 01 FEBRUARY 2007 DSC-3873/09 ...

Page 2

... IDT71V124SA, 3.3V CMOS Static RAM 1 Meg (128K x 8-Bit) Center Power & Ground Pinout Pin Configuration I SO32-2 7 I/O 1 SO32 SO32-4 GND SOJ and TSOP Top View ...

Page 3

... IDT71V124SA, 3.3V CMOS Static RAM 1 Meg (128K x 8-Bit) Center Power & Ground Pinout DC Electrical Characteristics (V = Min. to Max 0.2V Symbol Parameter I Dynamic Operating Current CC CS < Outputs Open Dynamic Standby Power Supply Current SB CS > Outputs Open Full Standby Power Supply Current (static) SB1 CS > ...

Page 4

... IDT71V124SA, 3.3V CMOS Static RAM 1 Meg (128K x 8-Bit) Center Power & Ground Pinout AC Electrical Characteristics (V = Min. to Max., Commercial and Industrial Temperature Ranges) DD Symbol Parameter READ CYCLE t Read Cycle Time RC t Address Access Time AA t Chip Select Access Time ACS (1) t Chip Select to Output in Low-Z ...

Page 5

... IDT71V124SA, 3.3V CMOS Static RAM 1 Meg (128K x 8-Bit) Center Power & Ground Pinout Timing Waveform of Read Cycle No. 1 ADDRESS OE CS HIGH IMPEDANCE DATA OUT Timing Waveform of Read Cycle No. 2 ADDRESS PREVIOUS DATA DATA OUT OUT NOTES HIGH for Read Cycle. 2. Device is continuously selected LOW. ...

Page 6

... IDT71V124SA, 3.3V CMOS Static RAM 1 Meg (128K x 8-Bit) Center Power & Ground Pinout Timing Waveform of Write Cycle No. 1 (WE Controlled Timing) ADDRESS (3) DATA OUT DATA IN Timing Waveform of Write Cycle No. 2 (CS Controlled Timing) ADDRESS DATA IN NOTES write occurs during the overlap of a LOW CS and a LOW WE. ...

Page 7

... IDT71V124SA, 3.3V CMOS Static RAM 1 Meg (128K x 8-Bit) Center Power & Ground Pinout Ordering Information IDT 71V124 Device Power Speed Package Type Process/ Temperature Range Blank Blank First generation or current die step H 7 6.42 Commercial and Industrial Temperature Ranges Commercial (0° ...

Page 8

... IDT71V124SA, 3.3V CMOS Static RAM 1 Meg (128K x 8-Bit), Center Power & Ground Pinout Datasheet Document History 11/22/99 Updated to new format Pg. 1–4, 7 Added Industrial Temperature range offerings Pg. 2 Added Recommended Operating Temperature and Supply Voltage table Pg. 6 Revised footnotes on Write Cycle No. 1 diagram Pg ...

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