TDA1305 Philips Semiconductors, TDA1305 Datasheet - Page 6

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TDA1305

Manufacturer Part Number
TDA1305
Description
Stereo 1fs data input up-sampling filter with bitstream continuous dual DAC BCC-DAC2
Manufacturer
Philips Semiconductors
Datasheet

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FUNCTIONAL DESCRIPTION
The TDA1305T CMOS digital-to-analog bitstream
converter incorporates an up-sampling filter and noise
shaper which increase the oversampling rate of 1f
data to 96f
normal speed mode. In the double speed mode the
oversample rate of 1f
(f
together with the 5-bit DAC, enables the filtering required
for waveform smoothing and out-of-band noise reduction
to be achieved by simple 1st order analog post filtering.
System clock and data input format
The TDA1305T accommodates slave mode only, this
means that in all applications the system devices must
Table 1 Data input format and system clock.
Note
1. Number of clock pulses within half an audio sample.
1995 Dec 08
sys
TEST1
Stereo 1fs data input up-sampling filter with
bitstream continuous dual DAC (BCC-DAC2)
= 384f
0
0
0
0
1
1
1
1
s
s
) or 64f
(f
sys
CLKS1
= 192f
0
0
1
1
0
0
1
1
s
(f
s
sys
input data is increased to 48f
s
) or 128f
= 256f
CLKS2
0
1
0
1
0
1
0
1
s
). This oversampling,
s
(f
sys
I
LSB fixed 16 bits
LSB fixed 18 bits
LSB fixed 20 bits
reserved
LSB fixed 16 bits
LSB fixed 18 bits
LSB fixed 20 bits
2
S up to 20 bits
= 256f
DATA INPUT FORMAT
s
) in the
s
input
s
6
provide a system clock of 256 or 384f
48 kHz). The system frequency is selectable by means of
pin CLKS1 and pin CLKS2. The SYSCLKO output (pin 16)
provides the system clock for external use.
The TDA1305T supports the following data input modes:
The input format is shown in Fig.3. Left and right
data-channel words are time-multiplexed.
I
(at f
LSB fixed serial format with data word lengths of 16, 18
and 20 bits (at f
MSB it is necessary to know how many bits are being
transmitted.
2
S-bus with data word lengths of up to 20 bits
sys
SYSTEM
CLOCK
= 256f
256f
384f
384f
384f
384f
384f
384f
s
s
s
s
s
s
s
s
).
sys
= 384f
CLOCK
s
DATA
>20
). As this format idles on the
24
24
24
32
32
32
Preliminary specification
(1)
s
TDA1305T
(f
s
= 32, 44.1 or
SYSCLKO
256f
384f
384f
384f
384f
384f
384f
s
s
s
s
s
s
s

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