MCP6S21 N/A, MCP6S21 Datasheet - Page 18

• Manufacturer Part Number: MCP6S21
• Description: Single-Ended, Rail-to-Rail I-O, Low Gain PGA
• Manufacturer: N/A

MCP6S21/2/6/8
5.0
The MCP6S21/2/6/8 PGAs use a standard SPI com-
patible serial interface to receive instructions from a
controller. This interface is configured to allow daisy
chaining with other SPI devices. There is an internal
POR (Power On Reset) that resets the registers under
low power conditions.
5.1
Chip Select (CS) toggles low to initiate communication
with these devices. The first byte of each SI word (two
bytes long) is the instruction byte, which goes into the
Instruction Register. The Instruction Register points the
second byte to its destination. In a typical application,
FIGURE 5-1:
FIGURE 5-2:
DS21117A-page 18
SCK
SCK
CS
SO
SO
CS
SI
SI
DIGITAL FUNCTIONS
SPI Timing
(first 16 bits out are always zeros)
(first 16 bits out are always zeros)
Serial bus sequence for the PGA; SPI 0,0 mode (see Figure 1-5).
Serial bus sequence for the PGA; SPI 1,1 mode (see Figure 1-6).
1
1
2
2
Instruction Byte
Instruction Byte
3
3
4
4
5
5
6
6
7
7
8
8
CS is raised after one word (16 bits) to implement the
desired changes. Section 5.3, “Registers”, covers
applications using multiple 16-bit words. SO goes low
after CS goes high; it has a push-pull output that does
not go into a high-Z state.
The MCP6S21/2/6/8 devices operate in SPI Modes 0,0
and 1,1. In 0,0 mode, the clock idles in the low state
(Figure 5-1) and, in 1,1 mode, the clock idles in the high
state (Figure 5-2). In both modes, SI data is loaded into
the PGA on the rising edge of SCK and SO data is
clocked out on the falling edge of SCK. In 0,0 mode, the
falling edge of CS also acts as the first falling edge of
SCK (see Figure 5-1). There must be multiples of 16
clocks (SCK) while CS is low or commands will abort
(see Section 5.3, “Registers”).
9
9
10
10
11
11
Data Byte
Data Byte
12
12
13
13
14
14
2003 Microchip Technology Inc.
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15
16
16