MCP6S21 N/A, MCP6S21 Datasheet - Page 20

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MCP6S21

Manufacturer Part Number
MCP6S21
Description
Single-Ended, Rail-to-Rail I-O, Low Gain PGA
Manufacturer
N/A
Datasheet

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MCP6S21/2/6/8
5.2.2
The amplifier can be programmed to produce binary
and decimal gain settings between +1 V/V and +32 V/V.
Register 5-2 shows the details. At the same time, differ-
ent compensation capacitors are selected to optimize
the bandwidth vs. slew rate trade-off (see Table 4-1).
REGISTER 5-2:
DS21117A-page 20
bit 7-3
bit 2-0
SETTING THE GAIN
GAIN REGISTER
Unimplemented: Read as ‘0’ (reserved for future use)
G2-G0: Gain Select Bits
000 = Gain of +1 (Default)
001 = Gain of +2
010 = Gain of +4
011 = Gain of +5
100 = Gain of +8
101 = Gain of +10
110 = Gain of +16
111 = Gain of +32
Legend:
R = Readable bit
-n = Value at POR
bit 7
U-x
U-x
U-x
W = Writable bit
’1’ = Bit is set
U-x
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared
U-x
W-0
G2
2003 Microchip Technology Inc.
x = Bit is unknown
W-0
G1
bit 0
W-0
G0

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