NCP1562B ON Semiconductor, NCP1562B Datasheet
NCP1562B
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NCP1562B Summary of contents
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... NCP1562A, NCP1562B High Performance Active Clamp/Reset PWM Controller The NCP1562x is a family of voltage mode controllers designed for dc−dc converters requiring high−efficiency and low parts count. These controllers incorporate two in phase outputs with an overlap delay to prevent simultaneous conduction and facilitates soft switching ...
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Disable start I inhibit 16 V AUX C AUX + + − AUX(on) − AUX(off1) V AUX(off2 UVOV UVOV R2 Detector V ref Oscillator 500 ...
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... CS Overcurrent sense input. If the CS voltage exceeds 0.2 V (or 0 the NCP1562B) the converter operates in cycle−by−cycle current limit. Once a current limit pulse is detected, the cycle skip timer is enabled. Internal leading edge blanking pulse prevents nuisance triggering during normal operation. ...
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PIN FUNCTION DESCRIPTION (continued) Pin Symbol 15 OUT1 Main output of the PWM Controller. OUT1 has a source resistance of 4.0 W (typ.) and a sink resistance of 2.5 W (typ.). OUT1 is designed to handle up to 2.5 A. ...
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MAXIMUM RATINGS (Notes 1 and 2) Line Voltage Auxiliary Supply, OUT1, OUT2 All Other Inputs/Outputs Voltage All Other Inputs/Outputs Current 5.0 V Reference Output Current 5.0 V Reference Output Voltage OUT1 Peak Output Current (D = 2%) OUT2 Peak Output ...
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ELECTRICAL CHARACTERISTICS R = 13 470 pF AUX 0.1 mF 29.4 kW 470 pF. For typical values T REF FF FF Characteristic STARTUP CONTROL ...
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... AUX kW 5.0 kW 0.1 mF SYNC REF 125°C, unless otherwise noted.) Characteristic CURRENT LIMIT AND THERMAL SHUTDOWN Cycle–by–Cycle Threshold Voltage (V out NCP1562A NCP1562B Propagation Delay to Output ( 1.0 V, LEB Disabled ILIM out T = 25_C –40_C to 125_C J Thermal Shutdown Threshold (Junction Temperature Increasing, Note 4) ...
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ELECTRICAL CHARACTERISTICS open 13.3 kW AUX kW 5.0 kW 0.1 mF SYNC REF 125°C, unless otherwise noted.) Characteristic SYNCHRONIZATION ...
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T , JUNCTION TEMPERATURE (°C) J Figure 2. Startup Circuit Inhibit Voltage Threshold vs. Junction Temperature 0.2 ...
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UVOV out1 out2 2 UVOV UVOV −50 − ...
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... SS Reset 125 100 −50 − JUNCTION TEMPERATURE (°C) J Figure 13. FF Offset and SS Reset Voltages vs. Junction Temperature 550 NCP1562B 500 450 400 350 300 250 NCP1562A 200 150 −50 − JUNCTION TEMPERATURE (°C) J Figure 15. Current Limit Threshold Voltage vs ...
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V 130 120 110 100 −50 − JUNCTION TEMPERATURE (°C) J Figure 18. Cycle Skip Charge Current vs. Junction Temperature 3.5 3.4 3.3 3.2 3.1 UPPER THRESHOLD ...
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C = 150 pF T 600 500 C = 220 pF T 400 300 200 100 C = 470 TIMING RESISTOR (kW) T Figure 24. Oscillator Frequency vs. ...
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AUX SOURCE out1 SINK out1 1 0 −50 − JUNCTION TEMPERATURE (°C) J ...
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The NCP1562x is a family of voltage mode controllers designed for dc−dc converters requiring high−efficiency and low parts count. These controllers incorporate two in phase outputs with an adjustable overlap delay. The main output is designed for driving a forward ...
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... Cycle−by−Cycle In cycle−by−cycle, the conduction period ends once the voltage on the CS pin reaches the current limit voltage threshold (V ). The NCP1562A has a V ILIM and the NCP1562B has 0.5 V. ILIM V ILIM CS V CSKIP(peak) ...
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... C CSKIP Figure 38. External Latch Implemented using ON Semiconductor’s MiniGatet Buffer The latch in Figure 38 consists of a TTL level tri−state output buffer from ON Semiconductor’s MiniGatet family. The enable (OE) and output (OUTY) terminals are connected to CSKIP and the V CC connected The output of the buffer high REF impedance mode when OE is low ...
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V AUX(on) V AUX(off1) V AUX V inhibit V UVOV V REF out1 The startup regulator is disabled by biasing This feature allows the NCP1562 to operate from AUX(on) an independent 12 V supply. ...
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This architecture allows both the UV and OV levels to be set independently. Both the UV and OV detectors have a 100 mV hysteresis. The line voltage is sampled using a resistor divider as shown in Figure 42. ...
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The minimum value determined by the FF FF Ramp discharge current (I ). The current through R FF( should be at least ten times smaller than I RFF sharp FF Ramp transition. Equations 3 and ...
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The output overlap delay is adjusted by connecting a resistor from the t pin to ground. The overlap delay proportional minimum delay obtained by grounding the ...
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... Application Information C Ramp Semiconductor provides an electronic design tool, a demonstration board and an application note to facilitate design of the NCP1562 and reduce development cycle time. All the tools can be downloaded or ordered at www.onsemi.com. The electronic design tool allows the user to easily ...
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Figure 51. Circuit Schematic ...
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... ORDERING INFORMATION Device NCP1562ADBR2G NCP1562BDBR2G NCP1562ADR2G NCP1562BDR2G †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D. Package Current Limit TSSOP−16 200 mV (Pb−Free) TSSOP−16 500 mV (Pb−Free) SO− ...
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K 16X REF 0.10 (0.004) 0.15 (0.006 L PIN 1 IDENT. 1 0.15 (0.006 −V− C 0.10 (0.004) −T− SEATING D PLANE PACKAGE DIMENSIONS TSSOP−16 DT SUFFIX CASE 948F−01 ISSUE ...
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... SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada Fax: 303− ...