NCP5214A ON Semiconductor, NCP5214A Datasheet
NCP5214A
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NCP5214A Summary of contents
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... NCP5214A 2−in−1 Notebook DDR Power Controller The NCP5214A 2−in−1 Notebook DDR Power Controller is specifically designed as a total power solution for notebook DDR memory system. This IC combines the efficiency of a PWM controller for the VDDQ supply with the simplicity of linear regulators for the VTT termination voltage and the buffered low noise reference ...
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... VTT COUT2 Ceramic FBVTT VTTGND 5VCC VCCA VREF VTTREF 0 DDQREF AGND NCP5214A OCDDQ BOOST VCCP TGDDQ SWDDQ NCP5214A BGDDQ PGND1 COMP CZ1 RZ1 FBDDQ VTTI Figure 1. Typical Application Diagram http://onsemi.com 2 RL1 5VCC 4 (Battery/ Adapter) M1 VDDQ L 1 ...
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... PGOOD OSC PGND VOCDDQ Adaptive Ramp + − SC2PWR VTTI Deadband Control + − VTTREF SC2GND + VTTREF − COUT3 GND AGND NCP5214A VREFGD THERMAL TSD VDDQEN SHUTDOWN VTTEN FPWM CONTROL VCCAGD LOGIC FAULT INREGDDQ ILIM + − VDDQ PWM FBDDQ LOGIC SWDDQ VDDQEN Power− ...
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... VDDQ regulator high−side gate driver supply. 21 BGDDQ Gate driver output for VDDQ regulator low−side N−Channel power FET. 22 PGND Power ground for the VDDQ regulator. 23 THPAD Copper pad on bottom of IC used for heatsinking. This pin should be connected to the ground plane un- der the IC. NCP5214A Description http://onsemi.com 4 ...
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... Human Body Model (HBM) ≤2.0 kV per JEDEC standard: JESD22–A114 except Pin 17 which is ≤ 1 kV. Machine Model (MM) ≤200 V per JEDEC standard: JESD22–A115 except Pin 17 which is ≤ 150 V. 2. Latchup Current Maximum Rating: ≤150 mA per JEDEC standard: JESD78. 3. Pin 16 (OCDDQ) must be pulled high to VIN through a resistor. NCP5214A Symbol ...
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... Ratio IN OCDDQ Pin Current Sink OCDDQ Pin Current Sink Temperature Coefficient Minimum On Time Maximum Duty Cycle Soft−Start Current Overvoltage Trip Threshold Undervoltage Trip Threshold 4. Guaranteed by design, not tested in production. NCP5214A ( −40 to 85_C CCA CCP = 25_C.) A Symbol ...
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... Soft−Start Source Current Limit Maximum Soft−Start Time V OUTPUT TTREF V Source Current TTREF V Accuracy Referred to 1/2V TTREF DDQREF 5. Guaranteed by design, not tested in production. NCP5214A (continued −40 to 85_C Symbol Test Conditions GAIN (Note 5) Ft COMP_GND = 220 nF, 1 Series (Note 5) ...
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... FPWM Pin Threshold High FPWM Pin Threshold Low FPWM Pin Input Current PGOOD Pin ON Resistance PGOOD Pin OFF Current PGOOD LOW−to−HIGH Hold Time, for Guaranteed by design, not tested in production. NCP5214A = −40 to 85_C CCA CCP = 25_C ...
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... T , AMBIENT TEMPERATURE (°C) A Figure 5. VCCA Shutdown Current vs. Ambient Temperature 0.90 0.85 0.80 0.75 0.70 −40 − AMBIENT TEMPERATURE (°C) A Figure 7. VDDQ Feedback Voltage vs. Ambient Temperature NCP5214A 1.0 0.8 0.6 0.4 0.2 0 −40 − AMBIENT TEMPERATURE (°C) A Figure 4. VCCA Quiescent Current in S3 vs. Ambient Temperature 450 425 400 375 350 ...
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... Figure 11. VTT Output Voltage (DDR) vs. VTT Output Current 1.260 1.255 1.250 1.245 V = 2.5 V DDQ T = 25°C A 1.240 VTTR OUTPUT CURRENT (mA) VTTR Figure 13. VTTR Output Voltage (DDR) vs. VTTR Output Current NCP5214A 1.810 1.805 1.800 1.795 V = 1.8 V DDQ S0 Mode T = 25°C A 1.790 0.94 0.93 0.92 0.91 ...
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... Figure 15. VDDQ Efficiency (DDR) vs. VDDQ Output Current VIN VDDQ VTT VTTR VDDQEN = High; VTTEN = High; VIN = Figure 17. Power−Up Waveforms VDDQEN VDDQ VTTR PGOOD VDDQEN = Figure 19. VDDQ, VTTR Start−Up Waveforms NCP5214A 100 ...
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... IVDDQ = 50 mA, IVTT = 100 mA, IVTTR = 5 mA Figure 23. S0−S3−S0 Transition Waveforms VDDQ VTT VTTR IVDDQ IVDDQ = 0 A−7 A, IVTT = 1.5 A, IVTTR = 15 mA Figure 25. VDDQ Load Transient NCP5214A VTTEN 5V/div VTT 1V/div 500mA/div IVTTI VDDQEN = High; VTT Loaded with 4 GND Figure 22. VTT Shutdown Waveforms ...
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... IVDDQ = 0 A, IVTT = 0 A, IVTTR = 0 mA, VIN = Figure 29. Line Transient 7V to 20V at No Load VDDQ VTT VTTR VIN IVDDQ = 10A, IVTT = 1.5A, IVTTR = 15mA, VIN = 7V to 20V Figure 31. Line Transient 7V to 20V at Full Load NCP5214A VDDQ 100mV/div VTT 50mV/div VTTR 50mV/div IVTT 2A/div IVDDQ = 8 A, IVTT = − ...
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... IVDDQ = 8 A, VTT shorts to ground, IVTTR = 15 mA Figure 33. VTT Short Circuit to Ground and Recovery VDDQ, 1V/div VSWDDQ, 10V/div VIN, 20V/div Figure 35. VDDQ OCP by Short Circuit to Ground Figure 37. VDDQ OCP by Start into a Short NCP5214A VDDQ 100mV/div VTT 1V/div VTTR 50mV/div IVTT 5A/div IVDDQ = 8 A, VTT shorts to VDDQ, IVTTR = 15 mA Figure 34 ...
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... General The NCP5214A 2−in−1 Notebook DDR Power Controller combines the efficiency of a PWM controller for the VDDQ supply, with the simplicity of using a linear regulator for the VTT termination voltage power supply. The VDDQ output can be adjusted through the external potential divider, while the VTT is internally set to track half VDDQ ...
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... The VTT regulator will have an internal soft−start when it is transited from disable to enable. During the VTT soft−start, a current limit is used as a NCP5214A current source to charge up the VTT output capacitor. The current limit is initially 1.0 A during VTT soft−start then increased to 2 ...
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... When the VDDQ output is above 106% but below 130% of the nominal regulation output voltage, the controller turns off the high−side MOSFET and turns on the low−side NCP5214A MOSFET to discharge the excessive output voltage. When the VDDQ output voltage goes back down to the nominal regulation voltage, normal switching cycles are resumed ...
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... VDDQ of 3.0 V. VTTEN goes and VTTREF go into HIGH, VTT is enabled normal mode. but not activated until VDDQ is good. Figure 38. Powerup and Powerdown Timing Diagram NCP5214A VTT in H−Z VTT Soft−start X 200 VTTEN goes LOW to activate S3 mode and to turn off VTT. ...
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... For steady output ripple voltage, both ESR and capacitance of the output capacitor are the contributing factors, however, the capacitor ESR is the dominant factor. The output ripple voltage is calculated as follows: I L(ripple) V ripple + I L(ripple) ESR ) NCP5214A APPLICATION INFORMATION V ripple + I L(ripple) where I L(ripple) and C is the output capacitance. ...
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... LOAD(max) The DC current rating of the inductor should be about 1.2 times of the peak inductor current at maximum output load current. Therefore, the maximum DC current rating of the inductor can be obtained by: I L(rating) + 1.2 I L(peak) NCP5214A where I L(peak) current which is determined by: I L(peak LOAD(max) ) (eq. 11) V OUT (eq ...
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... LC filter, Type III compensation network is required to obtain the desired close loop bandwidth and phase boost with unconditional stability. The NCP5214A PWM modulator, output LC filter and Type III compensation network are shown in Figure 39. The output LC filter has a double pole and a single zero. ...
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... Figure 40. Asymptotic Bode Plot of the Converter Gain NCP5214A sufficient phase margin for stability. The bandwidth of close loop gain should be less than 50% of the switching frequency and the compensation gain should be bounded by the error amplifier open loop gain. NCP5214A VBOOST Q1 TGDDQ VDDQ SWDDQ ...
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... The output voltage of the buck regulator can be adjusted by the feedback resistor divider formed by R the value selected when determining the 1 compensation components, the value of R by: NCP5214A By using the above equations and guidelines, the compensation components values can be determined by the 1 (eq. 28) equations below: L ...
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... VTT linear regulator high−side MOSFET, and the maximum VTT output current with VTT within regulation window will also be reduced if the external voltage is lower than VDDQ. Besides, the VTTI pin input must be bypassed NCP5214A to VTTGND with at least capacitor if external voltage source is used. Design Example A design example of a VDDQ bulk converter with the (eq ...
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... OUT calculated as: 2p 100 kHz NCP5214A Second, the ESR required to meet the transient load undershoot requirement is considered, such that: Therefore, the suitable ESR smaller, and the value of 7 selected for more design margin and better performance. Then, two same SP−Caps or POSCAPs ...
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... Since a 4.3 kW resistor is chosen as the high−side resistor R , the resistance value of low−side resistor R 1 calculated by 0.8 4 3.44 kW 1.8 V−0.8 V NCP5214A . Then, if the second zero break frequency is placed at the LC 3 filter’s double pole and the second pole is placed at half the switching frequency, the value (eq. 58) + 7.5 nF ...
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... NCP5214A vias with 0.6 mm hole−diameter to help heat dissipation and ensure good thermal capability recommended to use PCB with copper foil ...
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... Figure 41. Schematic Diagram of Evaluation Board NCP5214A C5 (option) U1 0.1 mF NCP5214A 16 OCDDQ R6 20 5.6 kW VCCP 4.7 mF MBR0530T1 BOOST D1 NTMS4700N C7 Q1 0.1 mF NCP5214A R7 18 TGDDQ 0 W N−CHANNEL 1 7.3 mW SWDDQ NTMS4107N Q2 R8 BGDDQ N−CHANNEL 22 PGND C14 30 V, 4.7 mW 100 pF 12 COMP C15 R9 4 ...
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... PCB Layout of Evaluation Board Figure 42. Silkscreen of Evaluation Board PCB Figure 44. Middle Layer1 of Evaluation Board PCB Layout Figure 46. Bottom Layer of Evaluation Board NCP5214A Figure 43. Top Layer of Evaluation Board PCB Layout Figure 45. Middle Layer2 of Evaluation Board PCB Layout PCB Layout http://onsemi.com 29 ...
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... Resistor, 130 W 1% 0603 Panasonic ERJ3EKF1300V Resistor, 4 0603 Panasonic ERJ3EKF4301V Resistor, 3. 0603 Panasonic ERJ3EKF3441V Resistor, 3 0603 Panasonic ERJ3GEYJ3R3V Header, single pin ON Semiconductor NCP5214A Shunt, 100 mil jumper http://onsemi.com 30 Mfg. & P/N Remark C3 & C20 are optional C5 is optional ...
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... Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada Email: orderlit@onsemi.com NCP5214A PACKAGE DIMENSIONS DFN22 MN SUFFIX CASE 506AF−01 ...