MC33342 ON Semiconductor, MC33342 Datasheet - Page 9

• Manufacturer Part Number: MC33342
• Description: (MC33340 / MC33342) Battery Fast Charge Controllers
• Manufacturer: ON Semiconductor

Testing
283 minutes to verify the operation of the 34 stage ripple
counter used in the timer. In order to significantly reduce the
test time, three digital switches were added to the circuitry
and are used to bypass selected divider stages. Entering each
of the test modes without requiring additional package pins
or affecting normal device operation proved to be
challenging. Refer to the timer functional block diagram in
Figure 11.
times speedup of the clock. This switch is enabled when the
V
fast charge time limit is accomplished by measuring the
propagation delay from when the V
1.0 V, to when the F/T output changes from a high−to−low
state. The 71, 106, 141, 177, 212, 247 and 283 will now
correspond to 8.1, 12.1, 16.2, 20.2, 24.3, 28.3 and 32.3 ms
delays. It is possible to enter this test mode during operation
if the equivalent battery pack voltage was to fall below 1.0 V.
This will not present a problem since the device would
normally switch from fast to trickle mode under these
Table 2. CONTROLLER OPERATING MODE TABLE
V
Timer Backup:
Temperature Backup:
Power Supply Voltage:
sen
>1.0 V and <2.0 V with
two consecutive −DV
events detected after the
initial holdoff period
Under normal operating conditions, it would take
Switch 1 bypasses 19 divider stages to provide a 524,288
sen
>1.0 V and <2.0 V
<1.0 V or >2.0 V
Within time limit
Beyond time limit
Within limits
Below lower limit
Above upper limit
V
V
CC
CC
input falls below 1.0 V. Verification of the programmed
Input Voltage:
Input Condition
>3.0 V and <18 V
>0.6 V and <2.8 V
(t
hold
)
The divided down battery pack voltage is within the fast charge voltage range. The charger switches
from trickle to fast charge mode as V
the timer and the overtemperature latch.
The battery pack has reached full charge and the charger switches from fast to a latched trickle mode.
A reset pulse must be applied for the charger to switch back to the fast mode. The reset pulse occurs
when entering the 1.0 V to 2.0 V window for V
The divided down battery pack voltage is outside of the fast charge voltage range. The charger
switches from fast to trickle mode.
The timer has not exceeded the programmed limit. The charger will be in fast charge mode if V
V
The timer has exceeded the programmed limit. The charger switches from fast to a latched
trickle mode.
The battery pack temperature is within the programmed limits. The charger will be in fast charge mode
if V
The battery pack temperature is below the programmed lower limit. The charger will stay in trickle
mode until the lower temperature limit is exceeded. When exceeded, the charger will switch from trickle
to fast charge mode.
The battery pack temperature has exceeded the programmed upper limit. The charger switches from
fast to a latched trickle mode. A reset signal must be applied and then released for the charger to
switch back to the fast charge mode. The reset pulse occurs when entering the 1.0 V to 2.0 V window
for V
This is the nominal power supply operating voltage range. The charger will be in fast charge mode if
V
The undervoltage lockout comparator will be activated and the charger will be in trickle mode. A reset
signal is applied to the timer and over temperature latch.
CC
sen
sen
, and temperature backup or timer backup are within their respective operating limits.
are within their respective operating limits.
sen
and V
sen
or when V
input falls below
CC
are within their respective operating limits.
CC
MC33340, MC33342
rises above 3.0 V.
http://onsemi.com
9
sen
conditions, and the relatively short variable time delay
would be transparent to the user.
times speedup of the clock. This switch is necessary for
testing the 19 stages that were bypassed when switch 1 was
enabled. Switch 2 is enabled when the V
1.0 V and the t1/T
Verification of the 19 stages is accomplished by measuring
a nominal propagation delay of 338.8 ms from when the V
input falls below 1.0 V, to when the F/T output changes from
a high−to−low state.
“B”. Section “A” bypasses 5 divider stages to provide a 32
times speedup of the V
the battery voltage. This speedup allows faster test
verification of two successive −DV events. Section “B”
bypasses 11 divider stages to provide a 2048 speedup of the
trickle mode holdoff timer. Switches 3A and 3B are both
activated when the t1/T
with respect to Pin 4.
Controller Operation
Switch 2 bypasses 11 divider stages to provide a 2048
Switch 3 is a dual switch consisting of sections “A” and
enters this voltage range, and a reset pulse is then applied to
sen
or when V
CC
ref
sen
rises above 3.0 V.
High input is biased at −100 mV.
ref
gate signal that is used in sampling
High input is biased at −100 mV
sen
input falls below
sen
and
sen