LM4681 National Semiconductor, LM4681 Datasheet - Page 15

• Manufacturer Part Number: LM4681
• Description: Stereo CLASS D Audio Power Amplifier
• Manufacturer: National Semiconductor

General Features
I
SPI Timing Diagram
SPI Operational Requirements
1. The maximum clock rate is 5MHz for the CLK pin.
2. CLK must remain logic-high for at least 100ns (t
the rising edge of CLK, and CLK must remain logic-low for at
least 100ns (t
3. Data bits are written to the DATA pin with the most
significant bit (MSB) first.
4. The serial data bits are sampled at the rising edge of CLK.
Any transition on DATA must occur at least 50ns (t
2
C Timing Diagrams
CL
) after the falling edge of CLK.
(Continued)
FIGURE 2. I
FIGURE 1. I
DS
CH
) before
) after
FIGURE 3.
2
C Timing Diagram
2
C Bus Format
15
the rising edge of CLK. Also, any transition on DATA must
occur at least 50ns (t
stabilize before the next rising edge of CLK.
5. ENABLE should be logic-low only during serial data trans-
mission.
6. ENABLE must be logic-low at least 50ns (t
first rising edge of CLK, and ENABLE has to remain logic-
low at least 50ns (t
7. If ENABLE remains logic-high for more than 50ns before
all 8 bits are transmitted then the data latch will be aborted.
EH
DH
) after the eighth rising edge of CLK.
) after the rising edge of CLK and
20118920
20118921
20118919
ES
) before the
www.national.com