MC54HC244A Motorola, MC54HC244A Datasheet

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MC54HC244A

Manufacturer Part Number
MC54HC244A
Description
Octal 3-State Noninverting Buffer/Line Driver/Line Receiver
Manufacturer
Motorola
Datasheet

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Octal 3-State Noninverting
Buffer/Line Driver/
Line Receiver
High–Performance Silicon–Gate CMOS
inputs are compatible with standard CMOS outputs; with pullup resistors,
they are compatible with LSTTL outputs.
used with 3–state memory address drivers, clock drivers, and other
bus–oriented systems. The device has noninverting outputs and two
active–low output enables.
2/97
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
ENABLES
OUTPUT
Motorola, Inc. 1997
The MC54/74HC244A is identical in pinout to the LS244. The device
This octal noninverting buffer/line driver/line receiver is designed to be
The HC244A is similar in function to the HC240A and HC241A.
Output Drive Capability: 15 LSTTL Loads
Outputs Directly Interface to CMOS, NMOS, and TTL
Operating Voltage Range: 2 to 6 V
Low Input Current: 1 A
High Noise Immunity Characteristic of CMOS Devices
In Compliance with the Requirements Defined by JEDEC Standard
No. 7A
Chip Complexity: 136 FETs or 34 Equivalent Gates
INPUTS
DATA
ENABLE A
ENABLE B
A1
A2
A3
A4
B1
B2
B3
B4
2
4
6
8
11
13
15
17
1
19
LOGIC DIAGRAM
1
PIN 20 = V CC
PIN 10 = GND
18
16
14
12
9
7
5
3
YA1
YA2
YA3
YA4
YB1
YB2
YB3
YB4
NONINVERTING
OUTPUTS
REV 7
MC54/74HC244A
20
20
ENABLE A
20
20
20
1
1
Z = high impedance
MC54HCXXXAJ
MC74HCXXXAN
MC74HCXXXADW
MC74HCXXXASD
MC74HCXXXADT
Enable A,
Enable B
ORDERING INFORMATION
GND
YB3
1
YB4
YB2
YB1
1
1
A1
A2
A3
A4
PIN ASSIGNMENT
FUNCTION TABLE
H
L
L
Inputs
1
2
3
4
5
6
7
8
9
10
A, B
H
X
L
CERAMIC PACKAGE
PLASTIC PACKAGE
TSSOP PACKAGE
SSOP PACKAGE
SOIC PACKAGE
20
19
18
17
16
15
14
13
12
11
CASE 940C–03
CASE 751D–04
CASE 948E–02
CASE 732–03
CASE 738–03
Outputs
DW SUFFIX
YA, YB
SD SUFFIX
DT SUFFIX
N SUFFIX
J SUFFIX
Ceramic
Plastic
SOIC
SSOP
TSSOP
H
Z
V CC
ENABLE B
YA1
B4
YA2
B3
YA3
B2
YA4
B1
L

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MC54HC244A Summary of contents

Page 1

... Chip Complexity: 136 FETs or 34 Equivalent Gates LOGIC DIAGRAM DATA INPUTS OUTPUT ENABLE A 19 ENABLES ENABLE B 2/97 Motorola, Inc. 1997 18 YA1 16 YA2 14 YA3 12 YA4 NONINVERTING OUTPUTS 9 YB1 7 YB2 5 YB3 3 YB4 PIN PIN 10 = GND 1 REV 7 MC54/74HC244A J SUFFIX CERAMIC PACKAGE 20 CASE 732– ...

Page 2

... SOIC Package: – from 125 _ C SSOP or TSSOP Package: – 6.1 mW from 125 _ C For high frequency or heavy load considerations, see Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D). RECOMMENDED OPERATING CONDITIONS Î Î Î Î ...

Page 3

... Current (per Package) Î Î Î Î NOTE: Information on typical parametric values and high frequency or heavy load considerations can be found in Chapter 2 of the Motorola High– Î Î Î Î Î Î Î Î Î Speed CMOS Data Book (DL129/D). ...

Page 4

... Data input pins. Data on these pins appear in noninverted form on the corresponding Y outputs, when the outputs are enabled. CONTROLS Enable A, Enable B (Pins 1, 19) Output enables (active–low). When a low level is applied MOTOROLA SWITCHING WAVEFORMS ENABLE 50 ...

Page 5

... DATA INPUT ENABLE A OR ENABLE B High–Speed CMOS Logic Data DL129 — Rev 6 LOGIC DETAIL TO THREE OTHER INVERTERS 5 MC54/74HC244A ONE OF 8 INVERTERS MOTOROLA ...

Page 6

... PLANE –A– –B– 20X 0.010 (0.25 18X K MOTOROLA OUTLINE DIMENSIONS J SUFFIX CERAMIC PACKAGE CASE 732–03 ISSUE SUFFIX PLASTIC PACKAGE CASE 738–03 ISSUE ...

Page 7

... MAX MIN MAX A 6.40 6.60 0.252 0.260 B 4.30 4.50 0.169 0.177 C ––– 1.20 ––– 0.047 D 0.05 0.15 0.002 0.006 F 0.50 0.75 0.020 0.030 G 0.65 BSC 0.026 BSC H 0.27 0.37 0.011 0.015 J 0.09 0.20 0.004 0.008 –W– J1 0.09 0.16 0.004 0.006 K 0.19 0.30 0.007 0.012 K1 0.19 0.25 0.007 0.010 L 6.40 BSC 0.252 BSC MOTOROLA ...

Page 8

... Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “ ...

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