MC54HC4060 Motorola, MC54HC4060 Datasheet - Page 4

MC54HC4060

Manufacturer Part Number

MC54HC4060

Description

14-Stage Binary Ripple Counter with Oscillator

Manufacturer

Motorola

Datasheet

1.MC54HC4060.pdf (10 pages)

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MOTOROLA

NOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).

* Osc In driven with external clock.

INPUTS

Osc In (Pin 11)

sition on this input advances the state of the counter. Osc In

may be driven by an external clock source.

Reset (Pin 12)

ronously resets the counter to its zero state (forcing all Q out-

puts low) and disables the oscillator.

TIMING REQUIREMENTS

MC54/74HC4060

OSC IN

Negative–edge triggering clock input. A high–to–low tran-

Active–high reset. A high level applied to this input asynch-

QN + 1

Symbol

t rec

t r , t f

t w

50%

Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î

10%

50%

Minimum Recovery Time, Reset Inactive to Osc In*

Minimum Pulse Width, Osc In

Minimum Pulse Width, Reset

Maximum Input Rise and Fall Times

90%

(Figure 2)

(Figure 1)

(Figure 2)

(Figure 1)

50%

t PLH

10%

50%

t f

t w

t PLH

t TLH

Figure 1.

Figure 3.

1/f max

(Input t r = t f = 6 ns)

t PHL

t r

t THL

t PHL

Parameter

SWITCHING WAVEFORMS

V CC

GND

V CC

GND

PIN DESCRIPTIONS

OUTPUTS

Q4 – Q10, Q12 – Q14 (Pins 7, 5, 4, 6, 14, 13, 15, 1, 2, 3)

frequency by 2 N . The user should note that Q1, Q2, Q3, and

Q11 are not available as outputs.

Osc Out 1, Osc Out 2 (Pins 10, 9)

Osc In and the external components to form an oscillator.

(See Figures 4 and 5). When Osc In is being driven with an

external clock source, Osc Out 1 and Osc Out 2 must be left

open circuited. With the crystal oscillator configuration in Fig-

ure 6, Osc Out 2 must be left open circuited.

Active–high outputs. Each QN output divides the oscillator

Oscillator outputs. These pins are used in conjunction with

Î Î Î Î

CLOCK

RESET

V CC

2.0

4.5

6.0

2.0

4.5

6.0

2.0

4.5

6.0

2.0

4.5

6.0

* Includes all probe and jig capacitance

Î Î Î Î Î Î Î Î Î

Î Î Î

Î Î Î Î Î Î Î Î Î

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Î Î Î Î Î Î Î Î Î

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– 55 to

t PHL

25 _ C

1000

100

500

400

DEVICE

UNDER

Figure 4. Test Circuit

TEST

Î Î Î Î

Guaranteed Limit

Figure 2.

50%

1000

High–Speed CMOS Logic Data

125

100

500

400

85 _ C

OUTPUT

t rec

50%

t w

Î Î Î Î

TEST POINT

50%

1000

125 _ C

150

120

500

400

DL129 — Rev 6

C L *

Î Î Î

Unit

V CC

GND

V CC

GND

MC54HC4060 Motorola, MC54HC4060 Datasheet - Page 4

MC54HC4060

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