ADL5604 Analog Devices, ADL5604 Datasheet - Page 19

• Manufacturer Part Number: ADL5604
• Description: 700 MHz To 2700 MHz 1 W RF Driver Amplifier
• Manufacturer: Analog Devices

ACPR AND EVM
All adjacent channel power ratio (ACPR) and error vector
magnitude (EVM) measurements were made using a single
W-CDMA carrier. For ACPR measurements, Test Model 1-64
was used, and for EVM measurements, Test Model 4 was used.
The signal is generated by a very low ACPR source and is
measured at the output by a high dynamic range spectrum
analyzer. The spectrum analyzer incorporates an instrument
noise correction function. Highly linear amplifiers were used to
boost the power levels
Figure 26 shows the plot of ACPR vs. P
on the same plot is the system ACPR. For power levels up to
11 dBm, an ACPR of 65 dBc or better can be achieved.
Figure 27 shows the ACPR vs. P
the same plot is the system ACPR. For power levels up to
11 dBm, an ACPR of 65 dBc or better can be achieved.
Figure 28 shows ACPR vs. P
same plot is the system ACPR. For power levels up to 12 dBm,
an ACPR of 65 dBc or better can be achieved. Figure 29 shows
the plot of EVM vs. P
11.2% for power levels up to 22 dBm.
Figure 30 shows the EVM vs. P
measured is 7.9% for power levels up to 24 dBm. Figure 31
shows the EVM vs. P
6.1% for power levels up to 22 dBm.
THERMAL CONSIDERATIONS
The ADL5604 is packaged in a thermally efficient 4 mm × 4 mm,
16-lead LFCSP. The thermal resistance from junction to air (θ
is 32.1
extracted assuming a standard 4-layer JEDEC board with nine
copper filled thermal vias. The thermal resistance from junction
to case (θ
frame package.
For the best thermal performance, it is recommended to add as
many thermal vias as possible under the exposed pad of the
LFCSP. The above thermal resistance numbers assume a
o
C/W. The thermal resistance for the product was
JC
) is 6
o
C/W where case is the exposed pad of the lead
OUT
OUT
at 2140 MHz. The EVM measured is
at 946 MHz. The EVM measured is
OUT
OUT
at 2140 MHz. Shown on the
OUT
at 1966 MHz. The EVM
at 1966 MHz. Shown on
OUT
at 946 MHz. Shown
Rev. 0 | Page 19 of 24
JA
)
minimum of nine thermal vias arranged in a 3 × 3 array with a
diameter of 8 mils and a pitch of 16 mils. Because the top and
bottom leads of the package are ground, the ground pattern on
the evaluation board is extended on the top and bottom to
improve thermal efficiency (see the Evaluation Board section).
SOLDERING INFORMATION AND RECOMMENDED
PCB LAND PATTERN
Figure 42 shows the recommended land pattern for the ADL5604.
To minimize thermal impedance, the exposed paddle on the
4 mm × 4 mm LFCSP package is soldered down to a ground
plane along with Pin 5 to Pin 8 and Pin 13 to Pin 16. To
improve thermal dissipation, nine thermal vias are arranged in
a 3 × 3 array under the exposed paddle. Areas above and below
the paddle are tied with regular vias. If multiple ground layers
exist, they should be tied together using vias. For more inform-
ation on land pattern design and layout, see the AN-772
Application Note, A Design and Manufacturing Guide for the
Lead Frame Chip Scale Package (LFCSP).
FILLED VIAs
FILLED VIAs
16 MIL
8 MIL
Figure 42. Recommended Land Pattern
RFIN
THERMAL VIAS
16
5
13
8
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RFOUT
ADL5604