HT45B0K Holtek Semiconductor, HT45B0K Datasheet - Page 13

• Manufacturer Part Number: HT45B0K
• Description: SPI to USB Bridge
• Manufacturer: Holtek Semiconductor

HT45B0K
SPI to USB Bridge
Rev 1.00
MISC Register
Name
POR
R/W
Bit
The MISC register contains the commands to control the desired endpoint FIFO action along with
the status to show the condition of the desired endpoint FIFO. The MISC register will be cleared by
a USB reset signal.
MISC Register
Bit 7
Bit 6
Bit 5
Bit 4~3
Bit 2
Bit 1
Unimplemented, read as “0”.
TX: Direction of data transfer between the MCU and the endpoint FIFO
0: no operation.
1: a zero-length packet is sent from the USB host.
READY: Endpoint FIFO Ready indication fl ag
0: the desired endpoint FIFO is not ready.
1: the desired endpoint FIFO is ready.
0: the data in the endpoint 0 FIFO is not SETUP token.
1: the data in the endpoint 0 FIFO is SETUP token.
CLEAR: clear requested FIFO
0: no operation.
1: clear the requested endpoint FIFO.
Bit 0
If this bit is set to 1, it indicates that a 0-sized packet is sent from a USB host. This bit
should be cleared by the application program or by the next valid SETUP token.
This bit is used to indicate whether the desired endpoint FIFO is ready to operate or not.
This bit is used to indicate whether the data in the Endpoint 0 FIFO is SETUP token or
not. It is set by hardware and cleared by fi rmware.
This bit is used by MCU to clear the requested FIFO, even if the FIFO is not ready. If
user wants to clear the current requested Endpoint FIFO, the CLEAR bit should be set to
1 to generate a positive pulse with 2μs pulse width and then clear this bit to zero.
LEN0: zero-length packet indication fl ag for Endpoint 0
SETCMD: SETUP command indication fl ag
LEN0
R/W
7
0
1: Error has occurred during endpoint 0 FIFO is accessed.
The ERR bit is used to indicate that there are some errors occurred during
endpoint 0 FIFO is accessed. This bit is set by SIE and should be cleared by
fi rmware.
ASET: Device Address update control
1: device address is updated after the device IN token data has been read
The ASET bit is used to confi gure the SIE to automatically update the device
address with the value stored in the AWR register. When this bit is set to 1
by firmware, the SIE will update the device address with the value stored
in the AWR register after the USB host has successfully read the data from
the device by IN token. Otherwise, when this bit is cleared to 0, the SIE will
update the device address immediately after an address is written to the AWR
register.
0: device address is updated immediately when the AWR register is written.
(SETUP stage fi nished).
READY
R
6
x
SETCMD
R/W
5
1
13
―
―
―
4
―
―
―
3
CLEAR
R/W
2
0
“x” means unknown.
R/W
TX
1
0
March 22, 2010
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R/W
0
0