HT45B0K Holtek Semiconductor, HT45B0K Datasheet - Page 14

• Manufacturer Part Number: HT45B0K
• Description: SPI to USB Bridge
• Manufacturer: Holtek Semiconductor

Rev 1.00
Check whether FIFOn can be read or not
Check whether FIFOn can be written or not
Read FIFOn sequence
Write FIFOn sequence
Read 0-sized packet sequence from FIFO0
Write 0-sized packet sequence to FIFOn
Bit 0
The MCU can communicate with the endpoint FIFO by setting the corresponding registers, whose
addresses are listed in the following table. After reading the current data, the next data will show
after 2μs, used to check the endpoint FIFO status and responds to the MISC register, if a read/write
action is still being implemented.
Some timing constrains are listed here. By setting the MISC register, the MCU can perform
reading, writing and clearing actions. There are some examples shown in the following for the
endpoint FIFO reading, writing and clearing.
Read or Write FIFOn Table (n=0~5)
Note *: There are 2μs existing between 2 reading actions or between 2 writing actions.
Actions
(MCU read data from the endpoint FIFO).
(MCU write data to the endpoint FIFO).
0: the data transfer from the endpoint FIFO to the MCU
1: the data transfer from the MCU to the endpoint FIFO
REQUEST: FIFO request control
0: no operation.
1: Request the desired FIFO.
This bit defi nes the direction of data transfer between the MCU and the endpoint FIFO.
When the TX bit is set to high, this means that the MCU desires to write data to the
endpoint FIFO. After the MCU write operation has been complete, this bit has to be
cleared to zero before terminating FIFO request to indicate the end of data transfer. For
a MCU read operation, this bit has to be cleared to zero to show that the MCU desires
to read data from the endpoint FIFO and has to be set to high before terminating FIFO
request to indicate the end of data transfer after the completion of MCU read operation.
This bit is used to request the operation of the desired FIFO. After selecting the desired
endpoint, the FIFO can be requested by setting this bit to high. After completion, this bit
has to be cleared to zero.
14
00H → 01H → delay 2μs, check 41H (ready) or 01H (not
ready) → 00H.
02H → 03H → delay 2μs, check 43H (ready) or 03H (not
ready) → 02H.
00H → 01H → delay 2μs, check 41H → read* from
FIFOn register and check not ready (01H) → 03H →
02H.
02H → 03H → delay 2μs, check 43H → write* to FIFOn
register and check not ready (03H) → 01H → 00H.
00H → 01H → delay 2μs, check 81H → clear LEN0 (01H)
→ 03H → 02H.
02H → 03H → delay 2μs → 01H → 00H.
MISC Setting Flow and Status
SPI to USB Bridge
HT45B0K
March 22, 2010
www.DataSheet4U.com