HT45R22E Holtek Semiconductor, HT45R22E Datasheet
HT45R22E
Related parts for HT45R22E
HT45R22E Summary of contents
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... HIRC, which requires no external components and which has three frequency selections, opens up a huge range of new application possibilities for this device, some of which may include remote control appliances, car reversing systems, level meters, consumer prod- ucts, household appliances subsystem controllers, etc. 1 www.DataSheet4U.com HT45R22E March 17, 2010 ...
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... Block Diagram The following block diagram illustrates the main functional blocks. Pin Assignment Note: Bracketed pin names indicate non-default pinout remapping locations. Rev. 1.00 2 www.DataSheet4U.com HT45R22E March 17, 2010 ...
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... EEPROM serial clock input pin ST CMOS General purpose I/O. Register enabled pull-up. SCOM Software controlled 1/2 bias LCD COM ST EEPROM serial data pin ST CMOS General purpose I/O. Register enabled pull-up. SCOM Software controlled 1/2 bias LCD COM ST CMOS General purpose I/O. Register enabled pull-up. 3 www.DataSheet4U.com HT45R22E March 17, 2010 ...
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... CMOS General purpose I/O. Register enabled pull-up and wake-up. OPA1 non-inverting input pin ST CMOS General purpose I/O. Register enabled pull-up and wake-up. Comparator non-inverting input pin PWR Power supply PWR Ground +4.0V Storage Temperature ............................ 125 C SS +0.3V Operating Temperature........................... Total............................................................ 100mA OH 4 www.DataSheet4U.com HT45R22E March 17, 2010 ...
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... SCOMC, ISEL[1:0]=00 17.5 SCOMC, ISEL[1:0]= SCOMC, ISEL[1:0]=10 70 SCOMC, ISEL[1:0]=11 140 3V No load 0.475 0.665 3V No load 0.475 0.995 3V No load 5 are measured with all I/O pins in input mode and tied to V DD4 5 www.DataSheet4U.com HT45R22E Ta=25 C Typ. Max. Unit 3.6 V 0.8 1.2 mA 0.8 2 0.3V V ...
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... Conditions DD 2.2V~3. Ta= Ta=0 C~ 2.2V~ Ta=0 C~ 3.6V 2.2V~ Ta=-20 C~70 C 12% 3.6V 3V Ta=25 C, R=120k * 2% 3V Ta=0 C~70 C, R=120k * 5% Ta=-20 C~ R=120k * 2.2V~ Ta=-20 C~70 C, 11% 3.6V R=120k * 2.2V~3. 5 www.DataSheet4U.com HT45R22E Ta=25 C Typ. Max. Unit 3 Ta=25 C Typ. Max. Unit 4095 kHz 4095 ...
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... After this period the first 4000 clock pulse is generated Only relevant for repeated 4000 START condition 0 200 4000 Time in which the bus must be free before a new 4700 transmission can start Noise suppression time =2.2V to 3.6V 7 www.DataSheet4U.com HT45R22E Ta=25 C Min. Typ. Max. Unit t 1024 SYS t 2 SYS ...
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... DD 3V Without calibration OPOF[3:0]=1000B 3V By Calibration =0~V 1. load 1.8 2.5 R =1M, C =100p 3V 500 www.DataSheet4U.com HT45R22E Typ. Max. Unit 100 mV V/ms ms Max. Unit 300 -1. 400 s Max. Unit 0 ...
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... The requirement for this extra cycle should be taken into account by programmers in timing sensitive applications. System Clocking and Pipelining Instruction Fetching 9 www.DataSheet4U.com HT45R22E March 17, 2010 ...
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... SUB, SUBM, SBC, SBCM, DAA Logic operations: AND, OR, XOR, ANDM, ORM, XORM, CPL, CPLA Rotation RRA, RR, RRCA, RRC, RLA, RL, RLCA, RLC Increment and Decrement INCA, INC, DECA, DEC Branch decision, JMP, SZ, SZA, SNZ, SIZ, SDZ, SIZA, SDZA, CALL, RET, RETI 10 www.DataSheet4U.com HT45R22E 4 March 17, 2010 ...
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... Program Memory will be transferred to the user de- fined Data Memory register [m] as specified in the in- struction. The higher order table data byte from the Program Memory will be transferred to the TBLH special register. Any unused bits in this transferred higher order byte will be read www.DataSheet4U.com HT45R22E March 17, 2010 ...
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... Note that all table related instructions require two instruction cycles to complete their operation. Table Location Bits PC8 @ Table Location 12 www.DataSheet4U.com HT45R22E March 17, 2010 ...
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... Data Memory. Data Memory Structure Note: Most of the Data Memory bits can be directly manipulated using the SET [m].i and CLR [m].i with the exception of a few dedicated bits. The Data Memory can also be accessed through the memory pointer registers. 13 www.DataSheet4U.com HT45R22E March 17, 2010 ...
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... Registers is carried out, the actual address that the microcontroller is directed to is the address specified by the related Memory Pointer. The following example shows how to clear a section of four Data Memory loca- tions already defined as locations adres1 to adres4. Special Purpose Data Memory 14 www.DataSheet4U.com HT45R22E March 17, 2010 ...
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... If the contents of the status registers are important and if the interrupt rou- tine can change the status register, precautions must be taken to correctly save it. Note that bits 0~3 of the STATUS register are both readable and writeable bits. 15 www.DataSheet4U.com HT45R22E March 17, 2010 ...
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... SET [m].i and CLR [m].i instructions. The ability to change I/O pins from output to input and vice versa by manipu- lating specific bits of the I/O control registers during nor- mal program operation is a useful feature of these devices. 16 www.DataSheet4U.com HT45R22E R/W R/W x ...
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... WDTEN3~WDTEN0=1010. The WDT is enabled when either the WDT configuration option is enabled or when bits WDTEN3~WDTEN0 1010. Rev. 1. PFDEN1 PFDEN0 R/W R TBSEL1 TBSEL0 WDTEN3 WDTEN2 R/W R/W R/W R www.DataSheet4U.com HT45R22E LXTLP CLKMOD R/W R WDTEN1 WDTEN0 R/W R March 17, 2010 ...
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... EEPROM Data Memory The HT45R22E device contains an internal 8K capacity EEPROM memory with a 1024 8 bits structure. An EEPROM, which stands for Electrically Erasable Pro- grammable Read Only Memory its nature a non-volatile form of memory, with data retention even when its power supply is removed ...
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... The data word address lower four bits are internally in- cremented following the receipt of each data word. The higher data word address bits are not incre- mented, retaining the memory page row location. Byte Write Timing Page Write Timing 19 www.DataSheet4U.com HT45R22E March 17, 2010 ...
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... The sequential read operation is terminated when the microcontroller responds with a no ACK signal (high) followed by a stop condition. Current Read Timing Random Read Timing Sequential Read Timing 20 www.DataSheet4U.com HT45R22E March 17, 2010 ...
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... C1 and C2. The exact values of C1 and C2 should be selected in consultation with the Pins crystal or resonator manufacturer s specification. OSC1/ OSC2 OSC1 OSC1/ OSC2 XT1/ XT2* Crystal/Resonator Oscillator - HXT 21 www.DataSheet4U.com HT45R22E March 17, 2010 ...
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... Hz Crystal Recommended Capacitor Values LXT Oscillator Low Power Function The LXT oscillator can function in one of two modes, the Quick Start Mode and the Low Power Mode. The mode selection is executed using the LXTLP bit in the CTRL0 register. 22 www.DataSheet4U.com HT45R22E C1 C2 8pF 10pF March 17, 2010 ...
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... Note that CLKMOD is only valid in HIRC+LXT oscillator configuration. OSC1/OSC2 Configuration Operating Mode HXT Normal Run Slow Sleep Stop Operating Mode Control System Clock Configurations 23 www.DataSheet4U.com HT45R22E HIRC + LXT ERC HIRC HIRC LXT Run Run Run Run Stop Run Stop Stop Stop ...
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... No matter what the source of the wake-up event is, once a wake-up event occurs, there will be a time delay before normal program execution resumes. Consult the table for the related time. 24 www.DataSheet4U.com HT45R22E March 17, 2010 ...
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... Timer, successive executions of this instruction will have no effect, only the execution of a CLR WDT2 instruc- tion will clear the Watchdog Timer. Similarly after the CLR WDT2 instruction has been executed, only a suc- cessive CLR WDT1 instruction can clear the Watch- dog Timer. 25 www.DataSheet4U.com HT45R22E March 17, 2010 ...
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... WS2, WS1, WS0: WDT time-out period selection 8 000 WDTCK 9 001 WDTCK 10 010 WDTCK 11 011 WDTCK 12 100 WDTCK 13 101 WDTCK 14 110 WDTCK 15 111 WDTCK Rev. 1. WS2 R/W 1 Watchdog Timer 26 www.DataSheet4U.com HT45R22E 1 0 WS1 WS0 R/W R March 17, 2010 ...
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... It is recommended that this component is added for added ESD protection ** It is recommended that this component is added in environments where power line noise is significant External RES Circuit More information regarding external reset circuits is located in Application Note HA0075E on the Holtek website. 27 www.DataSheet4U.com HT45R22E March 17, 2010 ...
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... Clear after reset, WDT begins WDT counting Timer/Event Timer Counter will be turned off Counter The Timer Counter Prescaler will Prescaler be cleared Input/Output Ports I/O ports will be setup as inputs Stack Pointer will point to the top Stack Pointer of the stack 28 www.DataSheet4U.com HT45R22E March 17, 2010 ...
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... HT45R22E WDT Time-out (Idle/Sleep ...
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... PAC4 PAC3 PAPU5 PAPU4 PAPU3 PBC5 PBC4 PBC3 PBPU5 PBPU4 PBPU3 PCWK5 PCWK4 PCWK3 PCC5 PCC4 PCC3 PCPU5 PCPU4 PCPU3 30 www.DataSheet4U.com HT45R22E PAWK2 PAWK1 PAWK0 PAC2 PAC1 PAC0 PAPU2 PAPU1 PAPU0 PBC2 PBC1 PBC0 PBPU2 PBPU1 PBPU0 PCWK2 PCWK1 PCWK0 ...
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... I/O Pin Structures The diagrams illustrate the I/O pin internal structures. As the exact logical construction of the I/O pin may differ from these drawings, they are supplied as a guide only to assist with the functional understanding of the I/O pins. 31 www.DataSheet4U.com HT45R22E March 17, 2010 ...
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... When the device is in the Idle/Sleep Mode, various methods are available to wake the device up. One of these is a high to low transition of any of these pins. Single or multiple pins on Port A or Port C can be setup to have this function. Generic Input/Output Ports 32 www.DataSheet4U.com HT45R22E March 17, 2010 ...
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... Rev. 1.00 PA7 NMOS Input/Output Port PB Input/Output Port 33 www.DataSheet4U.com HT45R22E March 17, 2010 ...
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... Timer Control Register which is known as TnEG. The TnS bit selects the inter- nal clock source if used. 34 www.DataSheet4U.com HT45R22E March 17, 2010 ...
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... Clock Structure for Timer/Time Base 8-bit Timer/Event Counter 0 Structure 8-bit Timer/Event Counter 1 Structure Rev. 1.00 35 www.DataSheet4U.com HT45R22E March 17, 2010 ...
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... Timer internal clock= 000 001 010 011 100: f /16 TP 101: f /32 TP 110: f /64 TP 111: f /128 TP Rev. 1. T0S T0ON T0EG T0PSC2 R/W R/W R/W R which is provided for Timer 0, the Time-Base TP 36 www.DataSheet4U.com HT45R22E 1 0 T0PSC1 T0PSC0 R/W R March 17, 2010 ...
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... Active Edge Select bit, TnEG, which is bit 3 of the Timer Control Register, is low, the Timer/Event Counter will increment each time the external timer pin receives a low to high transition. If the TnEG is high, the counter Timer Mode Timing Chart 37 www.DataSheet4U.com HT45R22E Bit7 Bit6 0 1 ...
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... It should be noted that in this mode the Timer/Event , for the 8-bit Counter is controlled by logical transitions on the exter- nal timer pin and not by the logic level. When the Timer/Event Counter is full and overflows, an interrupt 38 www.DataSheet4U.com HT45R22E March 17, 2010 ...
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... PFD output, bit PA1 must be set high to activate the PFD. These output data bits can be used as the on/off control bit for the PFD outputs. Note that the PFD outputs will all be low if the output data bit is cleared to zero. PFD Function - Single Output 39 www.DataSheet4U.com HT45R22E March 17, 2010 ...
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... Timer Control Register. The Timer/Event Counter can be turned off in a similar way by clearing the same bit. This example program sets the Timer/Event Counters the timer mode, which uses the internal system clock as their clock source. 40 www.DataSheet4U.com HT45R22E March 17, 2010 ...
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... Comparator & Operational Amplifier Registers The internal Operational Amplifiers are fully under the control of internal registers, COPA0C, COPA1C, COPA2C, COPA3C, OPA0OC and OPA1OC. These control the enable/disable function, input path selection, gain control, polarity and calibration function. 41 www.DataSheet4U.com HT45R22E March 17, 2010 ...
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... OPAs and Comparator in this device. S12 EA0I A0X A0 To OPA0 interrupt S22 S23 R2 500K EA1I A1X A1 To OPA1 interrupt TC0 pin POL C debounce CX (COUT) 42 www.DataSheet4U.com HT45R22E CINTS[1:0] =00: rasing edge =01: falling edge =10: both edge Edge to interrupt control mux To timer 0 external clock input TMR0S March 17, 2010 ...
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... A1NS1~A1NS0: OPA1 Inverting input signal selection bits 00: A1N pin 01: A0X, the OPA0 internal output pin 10 11: Unimplemented Rev. 1. A0PS0 CPS2 CPS1 CPS0 R/W R/W R/W R A1G0 A1PS2 A1PS1 A1PS0 R/W R/W R/W R www.DataSheet4U.com HT45R22E 1 0 CNS1 CNS0 R/W R A1NS1 A1NS0 R/W R March 17, 2010 ...
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... CNC: PC0/CN pin pin or GPIO (PC0) control bit 0: PC0 pin 1: CN pin (I/O pull-high disable) Rev. 1. S22 S21 S13 S12 R/W R/W R/W R A1NC A0XC A0PC A0NC R/W R/W R/W R www.DataSheet4U.com HT45R22E 1 0 S11 CXC R/W R CPC CNC R/W R March 17, 2010 ...
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... OPP as the reference input Bit 3~0 A1OF3~A1OF0: Operational amplifier input offset voltage cancellation control bits Rev. 1. A0OFM A0RS A0OF3 A0OF2 R/W R/W R/W R A1OFM A1RS A1OF3 A1OF2 R/W R/W R/W R www.DataSheet4U.com HT45R22E A0OF1 A0OF0 R/W R A1OF1 A1OF0 R/W R March 17, 2010 ...
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... If the input signal is noise sensitive, then the better choice will be the longer de-bounce time. The designer could select the suitable de-bounce time according to the input signal. 46 www.DataSheet4U.com HT45R22E March 17, 2010 ...
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... Bit 1~0 CINTS1, CINTS0: comparator interrupt trigger type selection 00: falling edge 01: rising edge 10: both edge 11: reserved Rev. 1. CPOL COUT DBC1 DBC0 R/W R R/W R CPVRC TMR0S R/W R www.DataSheet4U.com HT45R22E CPCS1 CPCS0 R/W R CINTS1 CINTS0 R/W R March 17, 2010 ...
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... Main Program Interrupt Request or Interrupt Flag Set by Instruction N Main Automatically Disable Interrupt Program Clear EMI & Request Flag Wait for Instruction Cycles (it will set EMI automatically) Interrupt Flow 48 www.DataSheet4U.com HT45R22E Enable Bit Set ? Y ISR Entry RETI March 17, 2010 ...
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... EIF, will be automatically reset and the EMI bit will be automatically cleared to dis- able other interrupts. Note that any pull-high resistor connections on this pin will remain valid even if the pin is used as an external interrupt input. 49 www.DataSheet4U.com HT45R22E Edge Trigger Type March 17, 2010 ...
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... EMFI: Multi-function interrupt enable 0: disable 1: enable Bit 1 ETBI: Time Base event interrupt enable 0: disable 1: enable Bit 0 unimplemented, read as 0 Rev. 1. T0F EIF ET1I ET0I R/W R/W R/W R TBF EMFI R/W R www.DataSheet4U.com HT45R22E 1 0 EEI EMI R/W R ETBI R/W 0 March 17, 2010 ...
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... It is recommended that programs do not use the CALL subroutine instruction within the interrupt subroutine. 51 www.DataSheet4U.com HT45R22E 1 0 EA0I ECI R/W R/W 0 ...
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... The LCD COM driver enables a range of selections to be provided to suit the requirement of the LCD panel which is being used. The bias resistor choice is imple- mented using the ISEL1 and ISEL0 bits in the SCOMC register. 52 www.DataSheet4U.com HT45R22E O/P Level March 17, 2010 ...
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... System oscillator configuration: HXT, HIRC, ERC, HIRC + LXT 5 LVR function: enable or disable 6 LVR voltage: 2.10V 7 RES or PA7 pin function 8 SST: 1024 or 2 clocks (determine t 9 Internal RC: 4095kHz Rev. 1. ISEL0 SCOMEN COM3EN COM2EN R/W R/W R/W R =3V) DD Options /4 SYS for HIRC/ERC) SST 53 www.DataSheet4U.com HT45R22E COM1EN COM0EN R/W R March 17, 2010 ...
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... Application Circuits Note recommended that this component is added for added ESD protection recommended that this component is added in environments where power line noise is significant. Rev. 1.00 54 www.DataSheet4U.com HT45R22E March 17, 2010 ...
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... These instructions are the key to decision making and branching within the pro- gram perhaps determined by the condition of certain in- put switches or by the condition of internal data bits. 55 www.DataSheet4U.com HT45R22E March 17, 2010 ...
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... Table conventions: x: Bits immediate data m: Data Memory address A: Accumulator i: 0~7 number of bits addr: Program memory address Description 56 www.DataSheet4U.com HT45R22E Cycles Flag Affected AC, OV Note AC AC AC, OV ...
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... For the CLR WDT1 and CLR WDT2 instructions the TO and PDF flags may be affected by the execution status. The TO and PDF flags are cleared after both CLR WDT1 and CLR WDT2 instructions are consecutively executed. Otherwise the TO and PDF flags remain unchanged. Rev. 1.00 Description 57 www.DataSheet4U.com HT45R22E Cycles Flag Affected 1 None Note 1 None ...
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... ACC ACC AND x Affected flag(s) Z ANDM A,[m] Logical AND ACC to Data Memory Description Data in the specified Data Memory and the Accumulator perform a bitwise logical AND op- eration. The result is stored in the Data Memory. Operation [m] ACC AND [m] Affected flag(s) Z Rev. 1.00 58 www.DataSheet4U.com HT45R22E March 17, 2010 ...
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... The TO, PDF flags and the WDT are all cleared. Note that this instruction works in conjunc- tion with CLR WDT1 and must be executed alternately with CLR WDT1 to have effect. Re- petitively executing this instruction without alternately executing CLR WDT1 will have no effect. Operation WDT cleared TO 0 PDF 0 Affected flag(s) TO, PDF Rev. 1.00 addr 59 www.DataSheet4U.com HT45R22E March 17, 2010 ...
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... This instruction stops the program execution and turns off the system clock. The contents of the Data Memory and registers are retained. The WDT and prescaler are cleared. The power down flag PDF is set and the WDT time-out flag TO is cleared. Operation TO 0 PDF 1 Affected flag(s) TO, PDF Rev. 1. www.DataSheet4U.com HT45R22E March 17, 2010 ...
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... No operation is performed. Execution continues with the next instruction. Operation No operation Affected flag(s) None OR A,[m] Logical OR Data Memory to ACC Description Data in the Accumulator and the specified Data Memory perform a bitwise logical OR oper- ation. The result is stored in the Accumulator. Operation ACC ACC OR [m] Affected flag(s) Z Rev. 1.00 addr 61 www.DataSheet4U.com HT45R22E March 17, 2010 ...
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... The contents of the specified Data Memory are rotated left by 1 bit with bit 7 rotated into bit 0. The rotated result is stored in the Accumulator and the contents of the Data Memory re- main unchanged. Operation ACC.(i+1) ACC.0 [m].7 Affected flag(s) None Rev. 1.00 Stack Stack Stack [m]. 0~6) 62 www.DataSheet4U.com HT45R22E March 17, 2010 ...
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... Data in the specified Data Memory and the carry flag are rotated right by 1 bit. Bit 0 re- places the Carry bit and the original carry flag is rotated into bit 7. The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged. Operation ACC.i [m].(i+1 0~6) ACC [m].0 Affected flag(s) C Rev. 1.00 [m]. 0~6) 63 www.DataSheet4U.com HT45R22E March 17, 2010 ...
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... Set Data Memory Description Each bit of the specified Data Memory is set to 1. Operation [m] FFH Affected flag(s) None SET [m].i Set bit of Data Memory Description Bit i of the specified Data Memory is set to 1. Operation [m].i 1 Affected flag(s) None Rev. 1.00 [ www.DataSheet4U.com HT45R22E March 17, 2010 ...
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... The result is stored in the Accumulator. Note that if the result of subtraction is nega- tive, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1. Operation ACC ACC Affected flag(s) OV, Z, AC, C Rev. 1.00 0 [m] [ www.DataSheet4U.com HT45R22E March 17, 2010 ...
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... The low byte of the program code (last page) addressed by the table pointer (TBLP) is moved to the specified Data Memory and the high byte moved to TBLH. Operation [m] program code (low byte) TBLH program code (high byte) Affected flag(s) None Rev. 1.00 [m].7 ~ [m].4 [m].7 ~ [m].4 [m].3 ~ [m].0 66 www.DataSheet4U.com HT45R22E March 17, 2010 ...
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... Operation [m] ACC XOR [m] Affected flag(s) Z XOR A,x Logical XOR immediate data to ACC Description Data in the Accumulator and the specified immediate data perform a bitwise logical XOR operation. The result is stored in the Accumulator. Operation ACC ACC XOR x Affected flag(s) Z Rev. 1.00 67 www.DataSheet4U.com HT45R22E March 17, 2010 ...
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... Symbol Rev. 1.00 Dimensions in inch Min. Nom. 0.393 0.256 0.012 0.496 0.050 0.004 0.016 0.008 0 Dimensions in mm Min. Nom. 9.98 6.50 0.30 12.60 1.27 0.10 0.41 0. www.DataSheet4U.com HT45R22E Max. 0.419 0.300 0.020 0.512 0.104 0.012 0.050 0.013 8 Max. 10.64 7.62 0.51 13.00 2.64 0.30 1.27 0.33 8 March 17, 2010 ...
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... Symbol Rev. 1.00 Dimensions in inch Min. Nom. 0.393 0.256 0.012 0.598 0.050 0.004 0.016 0.008 0 Dimensions in mm Min. Nom. 9.98 6.50 0.30 15.19 1.27 0.10 0.41 0. www.DataSheet4U.com HT45R22E Max. 0.419 0.300 0.020 0.613 0.104 0.012 0.050 0.013 8 Max. 10.64 7.62 0.51 15.57 2.64 0.30 1.27 0.33 8 March 17, 2010 ...
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... Product Tape and Reel Specifications Reel Dimensions SOP 20W, SOP 24W (300mil) Symbol Description A Reel Outer Diameter B Reel Inner Diameter C Spindle Hole Diameter D Key Slit Width T1 Space Between Flange T2 Reel Thickness Rev. 1.00 Dimensions in mm 330.0 1.0 100.0 1.5 +0.5/-0.2 13.0 2.0 0.5 +0.3/-0.2 24.8 30.2 0.2 70 www.DataSheet4U.com HT45R22E March 17, 2010 ...
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... Carrier Tape Width P Cavity Pitch E Perforation Position F Cavity to Perforation (Width Direction) D Perforation Diameter D1 Cavity Hole Diameter P0 Perforation Pitch P1 Cavity to Perforation (Length Direction) A0 Cavity Length B0 Cavity Width K0 Cavity Depth t Carrier Tape Thickness C Cover Tape Width Rev. 1.00 Dimensions in mm +0.3/-0.1 24.0 12.0 0.1 1.75 0.10 11.5 0.1 +0.1/-0.0 1.5 +0.25/-0.00 1.50 4.0 0.1 2.0 0.1 10.8 0.1 13.3 0.1 3.2 0.1 0.30 0.05 21.3 0.1 Dimensions in mm 24.0 0.3 12.0 0.1 1.75 0.1 11.5 0.1 +0.10/-0.00 1.55 +0.25/-0.00 1.50 4.0 0.1 2.0 0.1 10.9 0.1 15.9 0.1 3.1 0.1 0.35 0.05 21.3 0.1 71 www.DataSheet4U.com HT45R22E March 17, 2010 ...
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... Holtek s products are not authorized for use as critical components in life support devices or systems. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information, please visit our web site at http://www.holtek.com.tw. Rev. 1.00 72 www.DataSheet4U.com HT45R22E March 17, 2010 ...