HT46RB50 Holtek Semiconductor, HT46RB50 Datasheet

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HT46RB50

Manufacturer Part Number
HT46RB50
Description
A/D Type USB 8-Bit MCU
Manufacturer
Holtek Semiconductor
Datasheet

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Technical Document
Features
General Description
This device is an 8-bit high performance RISC
architecture microcontroller designed for USB product
applications. It is particularly suitable for use in products
such as USB and/or SPI touch-panels, USB and/or SPI
Rev. 1.10
Tools Information
FAQs
Application Note
Operating voltage:
f
f
38 bidirectional I/O lines (max.)
1 interrupt input shared with an I/O line
One 16-bit programmable timer/event counter with
overflow interrupt
One 8-bit programmable timer/event counter with
overflow interrupt and 7 stage prescaler
Only crystal oscillator (6MHz or 12MHz)
Watchdog Timer
4096 15 program memory
192 8 data memory RAM
HALT function and wake-up feature reduce power
consumption
Up to 0.33 s instruction cycle with 12MHz system
clock at V
SYS
SYS
=6MHz: 2.2V~5.5V
=12MHz: 2.7V~5.5V
DD
=5V
A/D Type USB 8-Bit MCU
1
touch-pads, PS II joysticks, XBOX joysticks, USB Mice
keyboards and joystick. A HALT feature is included to
reduce power consumption.
6-level subroutine nesting
8 channels 10-bit resolution A/D converter
2-channel 8-bit PWM output shared with two I/O lines
SIO (synchronous serial I/O) function
Supports Interrupt, Control, Bulk transfer
USB 1.1 full speed function compatible
4 endpoints supported (endpoint 0 included)
Total FIFO size is 88 byte (8, 8, 8, 64 for EP0~EP3)
Bit manipulation instruction
15-bit table read instruction
63 powerful instructions
All instructions in one or two machine cycles
Low voltage reset function
28-pin SOP/SKDIP, 48-pin SSOP package
HT46RB50
September 7, 2006

Related parts for HT46RB50

HT46RB50 Summary of contents

Page 1

... USB product applications particularly suitable for use in products such as USB and/or SPI touch-panels, USB and/or SPI Rev. 1.10 HT46RB50 A/D Type USB 8-Bit MCU 6-level subroutine nesting 8 channels 10-bit resolution A/D converter 2-channel 8-bit PWM output shared with two I/O lines ...

Page 2

... Block Diagram Rev. 1.10 2 September 7, 2006 HT46RB50 ...

Page 3

... Serial interface, Master mode is output, Slave mode is input. Bidirectional I/O lines. Software instructions determine the CMOS output or Schmitt trigger input with pull-high resistor (determined by pull-high options: nibble option). The PE1 is pin-shared with CLK. CLK is a Serial interface se- rial clock input/output (Initial is input). 3 HT46RB50 September 7, 2006 ...

Page 4

... Total............................................................ 100mA OH Test Conditions V Conditions DD f =6MHz SYS f =12MHz SYS 5V No load, f =6MHz SYS 3V No load, f =12MHz SYS load, system HALT, USB suspended load, system HALT, USB suspended 5V 4 HT46RB50 Ta=25 C Min. Typ. Max. Unit 2.2 5.5 V 2.7 5 ...

Page 5

... V =0. Option 3.0V 2 5mA V33O Test Conditions Min. V Conditions DD 2.2V~5.5V 400 3.3V~5.5V 400 2.2V~5.5V 0 3.3V~5. Wake-up from HALT HT46RB50 Typ. Max. Unit 150 200 100 3.3 V 3.3 3.6 V LSB 0 ...

Page 6

... Program Counter S10 Program Counter S11~S0: Stack register bits @7~@0: PCL bits 6 HT46RB50 * ...

Page 7

... The activated level is indexed by the stack pointer (SP) and is neither readable nor writeable. Table Location * Table Location P11~P8: Current program counter bits 7 HT46RB50 * September 7, 2006 ...

Page 8

... Accumulator - ACC The accumulator is closely related to ALU operations also mapped to location 05H of the RAM and capable of operating with immediate data. The data movement between two data memory locations must pass through the accumulator. Rev. 1.10 RAM Mapping 8 September 7, 2006 HT46RB50 ...

Page 9

... INTC0) is set as well. After the interrupt is enabled, the stack is not full, and the external interrupt is active (INT pin), a subroutine call at location 04H oc- curs. The interrupt flag (EIF) and EMI bits are all cleared to disable other maskable interrupts. Function Status (0AH) Register 9 HT46RB50 September 7, 2006 ...

Page 10

... When the HT46RB50 receives a USB Suspend signal from the Host PC, the suspend line (bit0 of the USC) of the HT46RB50 is set and a USB interrupt is also trig- gered. Also when the HT46RB50 receives a Resume signal from the Host PC, the resume line (bit3 of the ) of the HT46RB50 is set and a USB interrupt is triggered ...

Page 11

... CLR WDT instruction will clear the WDT. In case CLR WDT1 and CLR WDT2 are chosen (i.e. CLRWDT times equal two), these two instructions must be executed to clear the WDT, otherwise, the WDT may reset the chip due to time-out. 11 HT46RB50 15 , the maximum time-out pe- which about 2.3s~4.7s. September 7, 2006 ...

Page 12

... Note: u stands for unchanged To guarantee that the system oscillator is started and stabilized, the SST (System Start-up Timer) provides an extra-delay of 1024 system clock pulses when the sys- tem awakes from the HALT state or during power up. (system clock 12 HT46RB50 RESET Conditions September 7, 2006 ...

Page 13

... HT46RB50 000H Disable Cleared Clear. After master reset, WDT begins counting Off Input mode Points to the top of the stack USB Reset USB Reset ...

Page 14

... HT46RB50 USB Reset USB Reset (Normal) (HALT) 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 ...

Page 15

... FFFFH, bit 8 bits timer will be FFH). Once an overflow occurs, the counter is reloaded from the timer/event counter preload register, and generates an interrupt re- quest flag (T0F; bit 5 of the INTC0, T1F; bit 6 of the INTC0). Timer/Event Counter 0 Timer/Event Counter 1 15 HT46RB50 September 7, 2006 ...

Page 16

... The bit0~bit2 of the TMR0C can be used to define the pre-scaling stages of the internal clock sources of timer/event counter. The definitions are as shown. The timer prescaler is also used as the PWM counter. Function TMR0C (0EH) Register 16 HT46RB50 September 7, 2006 ...

Page 17

... Some instructions first input data and then follow the output operations. For example, SET [m].i , CLR [m].i , CPL [m] , CPLA [m] read the entire port states into the CPU, execute the defined operations (bit-operation), and then write the results back to the latches or the accumulator. Input/Output Ports 17 HT46RB50 September 7, 2006 ...

Page 18

... DC which is the value of PWM.7~PWM.2. Group 2 is denoted by AC which is the value of PWM.1~PWM. (6+2) bits mode PWM cycle, the duty cycle of each modulation cycle is shown in the table. . SYS Parameter AC (0~3) Modulation cycle i (i=0~3) (6+2) PWM Mode (7+1) PWM Mode 18 HT46RB50 Duty Cycle DC+1 i< September 7, 2006 ...

Page 19

... A/D should be initialised by issuing a 6 EOCB START signal, otherwise the EOCB flag may have an undefined condi- tion. See Important note for A/D in- itialisation . Starts the A/D conversion Start 7 START 0 1= Reset A/D converter and set EOCB ADCR (32H) Register 19 HT46RB50 Function Function September 7, 2006 ...

Page 20

... PB5 PB4 PB3 PB6 PB5 PB4 AN3 PB6 PB5 AN4 AN3 PB6 AN5 AN4 AN3 AN6 AN5 AN4 AN3 Port B Configuration A/D Conversion Timing 20 HT46RB50 PB2 PB1 PB0 PB2 PB1 AN0 PB2 AN1 AN0 AN2 AN1 AN0 AN2 ...

Page 21

... ADRL register mov adrl_buffer,a ; save result to user defined register clr START set START ; reset A/D clr START ; start A Rev. 1. the A/D clock SYS /8 as the A/D clock SYS 21 HT46RB50 September 7, 2006 ...

Page 22

... Low voltage state has to be maintained in its original state for over 1ms, then after 1ms delay, the device enters the reset mode. Rev. 1.10 The relationship between V Note the voltage range for proper chip OPR operation at 4MHz system clock. Low Voltage Reset 22 HT46RB50 and V is shown below. DD LVR September 7, 2006 ...

Page 23

... SBDR Master clock sending started by writing SBDR Slave transmitter: data I/O started by clock received Slave receiver: data I/O started by clock received 23 HT46RB50 serial bus selection signal en- this bit is set data is written to data transferred or data received write data to TXRX buffer read from SBDR only ...

Page 24

... CLK= floating SBEN= 0 serial bus disabled; SCS= SDI= SDO= CLK= floating TRF is set by SIO and cleared by users. When data transfer (transmission and reception) is completed, TRF is set to generate SBI (serial bus interrupt). 24 HT46RB50 step 6 output data in TXRX go to step 6 September 7, 2006 ...

Page 25

... Rev. 1.10 25 HT46RB50 September 7, 2006 ...

Page 26

... The device with remote wake-up function can wake-up the USB Host by sending a wake-up pulse through RMWK (bit 1 of the USC). Once the USB Host receive the wake-up signal from the HT46RB50, it will send a Resume signal to the device. The timing is as follow: USB Interface The HT46RB50 has 4 Endpoints (EP0~EP3) ...

Page 27

... When this bit is set to 1 (set by SIE), it indicates that the endpoint 3 is accessed 3 EP3IF R/W and a USB interrupt will occur. When the interrupt has been served, this bit should be cleared by firmware. 4~7 Undefined bit, read as 0 Rev. 1.10 Function USC (20H) Definitions Function USR (21H) Definitions 27 HT46RB50 September 7, 2006 ...

Page 28

... Bit No. Label R/W Set by users when the related USB endpoints are stalled. They are cleared by 3~0 STL3~STL0 R/W USB reset and Setup Token event 7~4 Undefined bit, read as 0 Rev. 1.10 Function UCC (22H) Definitions Function AWR (23H) Definitions Function STALL (24H) Definitions 28 HT46RB50 September 7, 2006 ...

Page 29

... To tell that the desired FIFO is ready to work. 6 READY R (1=Ready to work; 0=Non ready to work) To tell that host sent a 0-sized packet to MCU. This bit must be cleared by read 7 LEN0 R/W action to corresponding FIFO. (1=Host sent a 0-sized packet) Rev. 1.10 Function SIES (25H) Definitions Function MISC (26H) Definitions 29 HT46RB50 September 7, 2006 ...

Page 30

... Read or Write FIFO Table Function Option 30 HT46RB50 September 7, 2006 ...

Page 31

... X1 can use 6MHz or 12MHz close to OSC1 and OSC2 as possible Components with * are used for EMC issue 22pF capacitance are used for resonator only Rev. 1.10 Option HT46RB50 September 7, 2006 ...

Page 32

... Rotate data memory left through carry Data Move MOV A,[m] Move data memory to ACC MOV [m],A Move ACC to data memory MOV A,x Move immediate data to ACC Bit Operation CLR [m].i Clear bit of data memory SET [m].i Set bit of data memory Rev. 1.10 Description 32 HT46RB50 Instruction Flag Cycle Affected 1 Z,C,AC,OV (1) 1 Z,C,AC,OV 1 Z,C,AC,OV 1 Z,C,AC,OV (1) 1 ...

Page 33

... The flags may be affected by the execution status. If the Watchdog Timer is cleared by executing the CLR WDT1 or CLR WDT2 instruction, the TO and PDF are cleared. Otherwise the TO and PDF flags remain unchanged. Rev. 1.10 Description 33 HT46RB50 Instruction Flag Cycle Affected 2 None (2) 1 None ...

Page 34

... Add the accumulator to the data memory Description The contents of the specified data memory and the accumulator are added. The result is stored in the data memory. Operation [m] ACC+[m] Affected flag(s) TO Rev. 1.10 PDF PDF PDF PDF PDF HT46RB50 September 7, 2006 ...

Page 35

... Program Counter+1 Program Counter Affected flag(s) TO CLR [m] Clear data memory Description The contents of the specified data memory are cleared to 0. Operation [m] 00H Affected flag(s) TO Rev. 1.10 PDF PDF PDF addr PDF PDF HT46RB50 September 7, 2006 ...

Page 36

... Each bit of the specified data memory is logically complemented (1 s complement). Bits which previously contained a 1 are changed to 0 and vice-versa. Operation [m] [m] Affected flag(s) TO Rev. 1.10 PDF PDF PDF PDF PDF HT46RB50 September 7, 2006 ...

Page 37

... Data in the specified data memory is decremented by 1, leaving the result in the accumula- tor. The contents of the data memory remain unchanged. Operation ACC [m] 1 Affected flag(s) TO Rev. 1.10 PDF (ACC.3~ACC.0)+6, AC1=AC (ACC.3~ACC.0), AC1=0 ACC.7~ACC.4+6+AC1,C=1 ACC.7~ACC.4+AC1,C=C PDF PDF PDF HT46RB50 September 7, 2006 ...

Page 38

... Move data memory to the accumulator Description The contents of the specified data memory are copied to the accumulator. Operation ACC [m] Affected flag(s) TO Rev. 1.10 Program Counter+1 PDF PDF PDF addr PDF PDF HT46RB50 September 7, 2006 ...

Page 39

... Data in the data memory (one of the data memories) and the accumulator perform a bitwise logical_OR operation. The result is stored in the data memory. Operation [m] ACC OR [m] Affected flag(s) TO Rev. 1.10 PDF PDF Program Counter+1 PDF PDF PDF PDF HT46RB50 September 7, 2006 ...

Page 40

... The contents of the data memory remain unchanged. Operation ACC.(i+1) ACC.0 [m].7 Affected flag(s) TO Rev. 1.10 Stack PDF Stack PDF Stack PDF PDF [m].i; [m].i:bit i of the data memory (i=0~6) PDF HT46RB50 September 7, 2006 ...

Page 41

... Bit 0 replaces the carry bit; the original carry flag is rotated into the bit 7 position. Operation [m].i [m].(i+1); [m].i:bit i of the data memory (i=0~6) [m]. [m].0 Affected flag(s) TO Rev. 1.10 PDF [m].i; [m].i:bit i of the data memory (i=0~6) PDF PDF PDF PDF HT46RB50 September 7, 2006 ...

Page 42

... Otherwise proceed with the next instruction (1 cycle). Operation Skip if ([m] 1)=0, ACC Affected flag(s) TO Rev. 1.10 PDF PDF PDF ([m] 1) PDF ([m] 1) PDF HT46RB50 September 7, 2006 ...

Page 43

... Other- wise proceed with the next instruction (1 cycle). Operation Skip if [m].i 0 Affected flag(s) TO Rev. 1.10 PDF PDF ([m]+1) PDF ([m]+1) PDF PDF HT46RB50 September 7, 2006 ...

Page 44

... The low-order and high-order nibbles of the specified data memory are interchanged, writ- ing the result to the accumulator. The contents of the data memory remain unchanged. Operation ACC.3~ACC.0 ACC.7~ACC.4 Affected flag(s) TO Rev. 1.10 PDF PDF PDF [m].7~[m].4 PDF [m].7~[m].4 [m].3~[m].0 PDF HT46RB50 September 7, 2006 ...

Page 45

... The low byte of ROM code (last page) addressed by the table pointer (TBLP) is moved to the data memory and the high byte transferred to TBLH directly. Operation [m] ROM code (low byte) TBLH ROM code (high byte) Affected flag(s) TO Rev. 1.10 PDF PDF PDF PDF PDF HT46RB50 September 7, 2006 ...

Page 46

... Logical XOR immediate data to the accumulator Description Data in the accumulator and the specified data perform a bitwise logical Exclusive_OR op- eration. The result is stored in the accumulator. The 0 flag is affected. Operation ACC ACC XOR x Affected flag(s) TO Rev. 1.10 PDF PDF PDF HT46RB50 September 7, 2006 ...

Page 47

... Package Information 28-pin SOP (300mil) Outline Dimensions Symbol Rev. 1.10 Dimensions in mil Min. Nom. 394 290 14 697 HT46RB50 Max. 419 300 20 713 104 September 7, 2006 ...

Page 48

... SKDIP (300mil) Outline Dimensions Symbol Rev. 1.10 Dimensions in mil Min. Nom. 1375 278 125 125 16 50 100 295 330 0 48 HT46RB50 Max. 1395 298 135 145 20 70 315 375 15 September 7, 2006 ...

Page 49

... SSOP (300mil) Outline Dimensions Symbol Rev. 1.10 Dimensions in mil Min. Nom. 395 291 8 613 HT46RB50 Max. 420 299 12 637 September 7, 2006 ...

Page 50

... Key Slit Width T1 Space Between Flange T2 Reel Thickness SSOP 48W Symbol Description A Reel Outer Diameter B Reel Inner Diameter C Spindle Hole Diameter D Key Slit Width T1 Space Between Flange T2 Reel Thickness Rev. 1.10 Dimensions in mm 330 1 62 1.5 13+0.5 0.2 2 0.5 24.8+0.3 0.2 30.2 0.2 Dimensions in mm 330 1 100 0.1 13+0.5 0.2 2 0.5 32.2+0.3 0.2 38.2 0.2 50 HT46RB50 September 7, 2006 ...

Page 51

... Carrier Tape Width P Cavity Pitch E Perforation Position F Cavity to Perforation (Width Direction) D Perforation Diameter D1 Cavity Hole Diameter P0 Perforation Pitch P1 Cavity to Perforation (Length Direction) A0 Cavity Length B0 Cavity Width K0 Cavity Depth t Carrier Tape Thickness C Cover Tape Width Rev. 1.10 Dimensions 0.3 12 0.1 1.75 0.1 11.5 0.1 1.5+0.1 1.5+0.25 4 0.1 2 0.1 10.85 0.1 18.34 0.1 2.97 0.1 0.35 0.01 21.3 51 HT46RB50 September 7, 2006 ...

Page 52

... Perforation Position F Cavity to Perforation (Width Direction) D Perforation Diameter D1 Cavity Hole Diameter P0 Perforation Pitch P1 Cavity to Perforation (Length Direction) A0 Cavity Length B0 Cavity Width K1 Cavity Depth K2 Cavity Depth t Carrier Tape Thickness C Cover Tape Width Rev. 1.10 Dimensions 0.3 16 0.1 1.75 0.1 14.2 0.1 2 Min. 1.5+0.25 4 0.1 2 0.1 12 0.1 16.2 0.1 2.4 0.1 3.2 0.1 0.35 0.05 25.5 52 HT46RB50 September 7, 2006 ...

Page 53

... Holtek s products are not authorized for use as critical components in life support devices or sys- tems. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information, please visit our web site at http://www.holtek.com.tw. Rev. 1.10 53 HT46RB50 September 7, 2006 ...

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