MAS3507D Micronas Intermetall, MAS3507D Datasheet

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MAS3507D

Manufacturer Part Number
MAS3507D
Description
Mpeg 1/2 Layer 2/3 Audio Decoder
Manufacturer
Micronas Intermetall
Datasheet

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Edition March 16, 2000
6251-459-3PD
MICRONAS
MAS 3507D
MPEG 1/2 Layer 2/3
Audio Decoder
PRELIMINARY DATA SHEET

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MAS3507D Summary of contents

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MICRONAS Edition March 16, 2000 6251-459-3PD PRELIMINARY DATA SHEET MAS 3507D MPEG 1/2 Layer 2/3 Audio Decoder ...

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MAS 3507D Contents Page Section Title 5 1. Introduction 5 1.1. Features 6 1.2. Application Overview 6 1.2.1. Multimedia Mode 6 1.2.2. Broadcast Mode 7 2. Functional Description of the MAS 3507D 7 2.1. DSP Core 7 2.2. Firmware (Internal ...

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PRELIMINARY DATA SHEET Contents, continued Page Section Title 18 3. Control Interfaces Bus Interface 18 3.1.1. Device and Subaddresses 19 3.2. Command Structure 19 3.2.1. The Internal Fixed Point Number Format 20 3.2.2. Conventions for ...

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MAS 3507D Contents, continued Page Section Title 39 4. Specifications 39 4.1. Outline Dimensions 40 4.2. Pin Connections and Short Descriptions 43 4.2.1. Pin Descriptions 43 4.2.1.1. Power Supply Pins 43 4.2.1.2. DC/DC Converter Pins 43 4.2.1.3. Control Lines 43 ...

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PRELIMINARY DATA SHEET MPEG 1/2 Layer 2/3 Audio Decoder Release Note: Revision bars indicate significant changes to the previous edition. This data sheet applies to MAS 3507D version G10 and following versions. 1. Introduction The MAS 3507D is a single-chip ...

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MAS 3507D 1.2. Application Overview The MAS 3507D can be applied in two major environ- ments: in multimedia mode or in broadcast mode. For both modes, the DAC 3550A fits perfectly to the requirements of the MAS 3507D ...

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PRELIMINARY DATA SHEET 2. Functional Description of the MAS 3507D 2.1. DSP Core The hardware of the MAS 3507D consists of a high performance RISC Digital Signal Processor (DSP) and appropriate interfaces (see Fig. 2–1). The internal pro- cessor works ...

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MAS 3507D 2.3. Program Download Feature This is an additional feature that is not required for the MPEG decoding function. The overall function of the MAS 3507D can be altered by downloading kWord program code into the ...

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PRELIMINARY DATA SHEET 2.5. Clock Management The MAS 3507D should be driven by a single clock at a frequency of 14.725 MHz possible to drive the MAS 3507D with other reference clocks (see Section 3.7.2.1. on page 36). ...

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MAS 3507D 2.6.4. Start-up Sequence The DC/DC converter starts from a minimum input voltage of 0.9 V. There should be no output load during startup. In case WSEN is active, the MAS 3507D is in the DSP operation mode. The ...

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PRELIMINARY DATA SHEET 2.7. Interfaces 2 The MAS 3507D uses control interface, 2 selectable serial input interfaces for MPEG bit stream (SDI, SDI parallel I/O interface (PIO) for MPEG- or ADPCM-data and a digital audio ...

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MAS 3507D 2.7.3. Parallel Input Output Interface (PIO) The parallel interface of the MAS 3507D uses the lines PI0...PI4, PI8, PI12...PI19, and several control lines. 2.7.3.1. PIO-DMA Input Mode By setting the PIO pin PI4 to “1”, the PIO-DMA input ...

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PRELIMINARY DATA SHEET 2.7.3.3. DMA Handshake Protocol The data transfer can be started after the EOD pin of the MAS 3507D is set to “high”. After verifying this, the controller signalizes the sending of data by activating the PR line. ...

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MAS 3507D 2.7.4.2. Mode 2:32 Bit/Sample (Inverted SOI) If the serial output generates 32 bits per audio sample, only the first 20 bits will carry valid audio data. The 12 trailing bits are set to zero by default (see Fig. ...

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PRELIMINARY DATA SHEET 2.8. Start-up Configuration Basic operation of the MAS 3507D is possible without controller interaction. Configuration and the most important status information are available by the PIO interface. The start-up configuration is selected according to the levels of ...

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MAS 3507D 2.9. Status Pins in SDI Input Mode After having read the start-up configuration, the PIO will be switched to ‘ P-mode’. In P-mode, the addi- tional PIO control lines (PR, PCS ) are evaluated. If the MPEG decoder ...

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PRELIMINARY DATA SHEET Table 2–10: Frame length in MPEG layer Frame Length s kHz Layer 44.1 26. 22.05 26. ...

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MAS 3507D 3. Control Interfaces 2 3. Bus Interface 3.1.1. Device and Subaddresses The MAS 3507D is controlled via the I interface. The IC is selected by transmitting the MAS 3507D device addresses. (see Table 3–1). Writing is ...

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PRELIMINARY DATA SHEET 2 Note C-Bus Start Condition from master C-Bus Stop Condition from master ACK = Acknowledge-Bit: LOW on I2C_DA from slave or master NAK = Not Acknowledge-Bit: HIGH on I2C_DA from ...

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MAS 3507D 3.2.2. Conventions for the Command Description The description of the various controller commands uses the following formalism: – A data value is split into 4-bit nibbles which are num- bered beginning with 0 for the least significant nib- ...

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PRELIMINARY DATA SHEET 3.3.2. Read Control Interface Data 1) send command dev_write data_write $ get ancillary data values dev_write data_read dev_read A d3, d2 (ancillary word 0) ....repeat for n ...

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MAS 3507D 3.3.6. Read Register 1) send command dev_write data_write $ get register value dev_write data_read dev_read d3, d2 d1,d0 r1, r0: register r d3...d0: data value in ...

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PRELIMINARY DATA SHEET 3.4. Protocol Description 3.4.1. Run Command S $3A ACK $68 ACK a3, a2 3.4.2. Read Control Interface Data Send Command S $3A ACK $68 ACK $3, x2 Get Ancillary Data Values S $3A ACK $69 ACK S ...

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MAS 3507D 3.4.5. Write to MAS 3507D D1 Memory S $3A ACK $68 ACK $B, $0 ACK n3, n2 ACK a3, a2 ACK d3, d2 ACK $0, $0 ACK d3, d2 ACK $0, $0 3.4.6. Read Register Send command S ...

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PRELIMINARY DATA SHEET Get memory values S $3A ACK $69 ACK S ACK d3, d2 ACK d1, d0 Wait ACK $0, $0 ACK $0, d4 ACK d3, d2 ACK d1, d0 Wait ACK d3, d2 ACK d1, d0 3.4.9. Default ...

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MAS 3507D 3.6. Register Table In Table 3–6, the internal registers that are useful for controlling the MAS 3507D are listed. They are acces- 2 sible by ‘register read/write’ commands (see Sec- tion 3.3. on page 20). Important ...

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PRELIMINARY DATA SHEET Table 3–7: DC/DC-converter switch frequency (Bits 8, 13..10 of DCCF-register) DCCF Value f 1) (hex) Bit 0CC00 156 kHz 0C800 160 kHz 0C400 163 kHz 0C000 167 kHz 04C00 171 kHz 04800 175 kHz ...

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MAS 3507D 3.6.2. Muting / Bypass Tone Control Address R/W Name $aa r/w Mute / Bypass Tone Control enable fast and simple mute functionality, set bit 0 in register $aa to ‘1’. Writing a ‘0’ deactivates ...

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PRELIMINARY DATA SHEET Table 3–9: Tone control registers Boost in Bass Treble dB (Reg. $6b) (Reg. $6f) +15 $61800 $5f800 +14 $5d400 $58400 +13 $58800 $51800 +12 $53800 $49c00 +11 $4e400 $42c00 +10 $48800 $3c000 +9 $42800 $35400 +8 $3c000 ...

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MAS 3507D 3.7. Memory Area 3.7.1. Status Memory The memory cells given in the following table should be accessed by the ‘read control interface data’ I (see Section 3.3.2. on page 21) because only the 16 LSBs of these memory ...

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PRELIMINARY DATA SHEET 3.7.1.2. MPEG Status 1 Address Offset R/W D0:$301 1 r The MPEG Status 1 contains the bits 15...11 of the MPEG header and some status bits. It will be set each frame, directly after the header has ...

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MAS 3507D 3.7.1.3. MPEG Status 2 Address Offset R/W D0:$302 2 r The MPEG Status 2 contains the 16 LSBs of the MPEG header. It will be set directly after synchronizing to the bit stream. Table 3–12: MPEG Status 2 ...

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PRELIMINARY DATA SHEET Table 3–12: MPEG Status 2 Bits Value/Name Emphasis %00 %01 %10 %11 3.7.1.4. CRC Error Counter Address Offset R/W D0:$303 3 r The counter will be increased by each CRC error ...

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MAS 3507D 3.7.1.6. Ancillary Data Address Offset R/W D0:$305 ... 5 r D0:$321 This memory field contains the ancillary data organized in words 16 bit each. The last ancillary bit transmitted in a frame is placed at bit ...

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PRELIMINARY DATA SHEET 3.7.2. Configuration Memory The configuration memory allows the controller advanced configuration possibilities, e.g. changing setups for the crystal frequency or changing the digital format of the serial audio output data interface. Table 3–15: Configuration memory area Address ...

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MAS 3507D 3.7.2.1. PLL Offset for 44/48 kHz Sampling Frequency Address R/W Name D0:$36d r/w PLLOffset48 D0:$36e r/w PLLOffset44 With these memory cells it is possible to choose other frequencies than the standard CLKI frequencies. Please note: – PLLOffset48 is ...

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PRELIMINARY DATA SHEET 3.7.2.2. Output Configuration Address R/W Name D0:$36f r/w OutputConfig The content of this memory cell depends on the start- up configuration and will be set by the firmware. Never- theless, the audio output interface is configurable by ...

Page 38

MAS 3507D left audio right audio Fig. 3–2: Digital volume matrix Table 3–21: Volume matrix conversion (dB into hexadecimal) Volume Hexa Volume (in dB) decimal (in dB) 0 80000 20 1 8DEB8 ...

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PRELIMINARY DATA SHEET 4. Specifications 4.1. Outline Dimensions 1 1 17.52 0.12 Fig. 4–1: 44-Pin Plastic Leaded Chip Carrier Package (PLCC44) Weight approximately 2.5 g Dimensions in mm ...

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MAS 3507D A1 Ball Pad Corner 0.8 1 0.8 = 4.8 7 Fig. 4–3: 49-Ball Plastic Ball Grid Array (PBGA49) Weight approximately 0.13 g Dimensions in mm 4.2. Pin Connections and ...

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PRELIMINARY DATA SHEET Pin No. Pin Name PMQFP PLCC PBGA Test Alias in () 44-pin 44-pin 49-ball PCS PI19 PI18 PI17 PI16 ...

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MAS 3507D Pin No. Pin Name PMQFP PLCC PBGA Test Alias in () 44-pin 44-pin 49-ball SIC PI4 PI3 PI2 PI1 PI0 ...

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PRELIMINARY DATA SHEET 4.2.1. Pin Descriptions 4.2.1.1. Power Supply Pins Connection of all power supply pins is mandatory for the function of the MAS 3507D. VDD VSS The VDD/VSS pair is internally connected with all digi- tal modules of the ...

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MAS 3507D PI19 DEMAND PIN When MAS 3507D is in multimedia mode it demands with PI19 = ’1’ for new input data. PI18 MPEG-IDEX PI17 MPEG-ID These pins mirror the according bits of the MPEG header (see Table 2–9 for ...

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PRELIMINARY DATA SHEET 4.2.1.8. Miscellaneous POR The Power On Reset pin is used to reset the digital parts of the MAS 3507D. POR is a low active signal. TE The TE pin is for production test only and must be ...

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MAS 3507D 4.2.3. Internal Pin Circuits TTLIN Fig. 4–6: Input pins PCS, PR Fig. 4–7: Input pin TE, DCEN Fig. 4–8: Input pins WSEN, POR Fig. 4–9: Input pin CLKI VDD P N VSS Fig. 4–10: Input/Output pins PI0...PI4, PI8, ...

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PRELIMINARY DATA SHEET 4.2.4. Electrical Characteristics 4.2.4.1. Absolute Maximum Ratings Symbol Parameter T Ambient Operating Temperature A T Storage Temperature S P Power dissipation MAX V Supply voltage SUP V Input voltage, all digital inputs Idig I Input current, all ...

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MAS 3507D Symbol Parameter Levels I Input Low Voltage IL27 @V = 2.5 V ... 3.6 V SUP I Input High Voltage IH36 @V = 2.5 V ... 3.6 V SUP I Input High Voltage IH33 @V = 2.5 V ...

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PRELIMINARY DATA SHEET 4.2.4.3. Characteristics ° 2.5 to 3.6 V, typ. values SUP cycle = 50% Symbol Parameter Supply Voltage I Current consumption SUP Digital Outputs and Inputs V ...

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MAS 3507D 2 4.2.4.3. Characteristics °C, V =2.5 to 3.6 V, typ. values SUP cycle = 50 % Symbol Parameter R Output resistance Bus ...

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PRELIMINARY DATA SHEET 2 4.2.4.3. Bus Characteristics – SDI °C, V =2.5 to 3.6 V, typ. values SUP cycle = 50 % Symbol Parameter Clock ...

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MAS 3507D 2 4.2.4.3. Characteristics – SDO ° 2.5 to 3.6 V, typ. values SUP cycle = 50 % Symbol Parameter Clock Output ...

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PRELIMINARY DATA SHEET 4.2.4.4. Firmware Characteristics ° 2.5 to 3.6 V, typ. values SUP cycle = 50 % Symbol Parameter Synchronization Times t Synchronization on MPEG Bit Streams mpgsync ...

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MAS 3507D 4.2.4.5. DC/DC Converter Characteristics ° 3.0 V, CLK A SUP Symbol Parameter V Minimum Start-Up Input IN1 Voltage V Minimum Operating Voltage IN2 V Output Voltage OUT dV /dV / ...

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PRELIMINARY DATA SHEET 4.2.4.6. Typical Performance Characteristics Efficiency vs. Load Current (Vout=3.5V) 100 3.0 V Vin Load Current (A) Efficiency vs. Load Current (Vout=2.7V) 100 Vin ...

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MAS 3507D Output Voltage vs. Input Voltage Iload=250mA 3.6 3.5 V 3.4 3.2 3 2.8 2.7 V 2.6 1.5 2 2.5 Input Voltage (V) Fig. 4–21: Output Voltage vs. Input Voltage Output Voltage vs. Load Current 3.6 3.4 ...

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PRELIMINARY DATA SHEET Maximum Load Current vs. Input Voltage 0.8 0.6 2.2V V out 0.4 0 Input Voltage (V) Fig. 4–23: Maximum Load Current vs. Input Voltage Micronas 6.0 3.5V 4.0 2.0 Vout= 3.5V 3.1V 2.7V 2.2V ...

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MAS 3507D 500.00 s/Div out 1 Load Current 200.0 mA/Div 2 Output Voltage 100.0 mV/Div / AC-coupled 3 Inductor Current 500.0 mA/Div Fig. 4–25: Load Transient-Response 5.00 ms/Div I = 100 ...

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PRELIMINARY DATA SHEET Micronas MAS 3507D 59 ...

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MAS 3507D 5. Data Sheet History 1. Preliminary data sheet: “MAS 3507D MPEG 1/2 Layer2/3 Audio Decoder”, Feb. 25, 1998, 6251-459-1PD. First release of the preliminary data sheet. 2. Preliminary data sheet: “MAS 3507D MPEG 1/2 Layer 2/3 Audio Decoder”, ...

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