DSP56F826 Motorola, DSP56F826 Datasheet
DSP56F826
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DSP56F826 Summary of contents
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... Semiconductor Products Sector Preliminary Technical Data DSP56F826 16-bit Digital Signal Processor • MIPS at 80MHz core frequency • DSP and MCU functionality in a unified, C-efficient architecture • Hardware DO and REP loops • MCU-friendly instruction set supports both DSP and controller functions: MAC, bit manipulation unit, 14 addressing modes • ...
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... One Serial Peripheral Interface with 4 pins (or four additional GPIO lines) • One Serial Peripheral Interface, or multiplexed with two Serial Communications Interfaces totalling 4 pins • Synchronous Serial Interface (SSI) with configurable six-pin port (or six additional GPIO lines) 2 data memory program memory DSP56F826 Preliminary Technical Data ...
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... The DSP56F826 supports program execution from either internal or external memories. Two data operands can be accessed from the on-chip Data RAM per instruction cycle. The DSP56F826 also provides two external dedicated interrupt lines, and General Purpose Input/Output (GPIO) lines, depending on peripheral configuration ...
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... Together, the SDK, CodeWarrior, and EVMs create a complete, scalable tools solution for easy, fast, and efficient development. 1.4 Product Documentation The four documents listed in Table 1 DSP56F826. Documentation is available from local Motorola distributors, Motorola semiconductor sales offices, Motorola Literature Distribution Centers, or online at www.motorola.com/semiconductors/. Table 1. DSP56F826 Chip Documentation Topic DSP56800 ...
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... Part 2 Signal/Connection Descriptions 2.1 Introduction The input and output signals of the DSP56F826 are organized into functional groups, as shown in and as illustrated in Figure 2. In Table 2. Functional Group Pin Allocations Power ( DDIO or Ground ( SSIO or PLL and Clock 1 Address Bus Data Bus Bus Control ...
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... TA1 (GPIOF1) Quad Timer A TA2 (GPIOF2) TA3 (GPIOF3) TCK TMS JTAG/OnCE TDI Port TDO TRST DE Figure 2. DSP56F826 Signals Identified by Functional Group 1. Alternate pin functionality is shown in parenthesis. 6 DSP56F826 Dedicated SSI Port or Address SPI1 Port or SCI0 Port or SPI0 Port SCI1 Port or SPI0 Port ...
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... Table 3. DSP56F826 Signal and Package Information for the 100 Pin LQFP All inputs have a weak internal pull-up circuit associated with them. These pull-up circuits are always enabled. Exceptions: 1. When owned by GPIO, then the pull-up may be disabled under software control. 2. TCK has a weak pull-down circuit always active. ...
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... Table 3. DSP56F826 Signal and Package Information for the 100 Pin LQFP All inputs have a weak internal pull-up circuit associated with them. These pull-up circuits are always enabled. Exceptions: 1. When owned by GPIO, then the pull-up may be disabled under software control. 2. TCK has a weak pull-down circuit always active. ...
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... Table 3. DSP56F826 Signal and Package Information for the 100 Pin LQFP All inputs have a weak internal pull-up circuit associated with them. These pull-up circuits are always enabled. Exceptions: 1. When owned by GPIO, then the pull-up may be disabled under software control. 2. TCK has a weak pull-down circuit always active. ...
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... Table 3. DSP56F826 Signal and Package Information for the 100 Pin LQFP All inputs have a weak internal pull-up circuit associated with them. These pull-up circuits are always enabled. Exceptions: 1. When owned by GPIO, then the pull-up may be disabled under software control. 2. TCK has a weak pull-down circuit always active. ...
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... Table 3. DSP56F826 Signal and Package Information for the 100 Pin LQFP All inputs have a weak internal pull-up circuit associated with them. These pull-up circuits are always enabled. Exceptions: 1. When owned by GPIO, then the pull-up may be disabled under software control. 2. TCK has a weak pull-down circuit always active. ...
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... Table 3. DSP56F826 Signal and Package Information for the 100 Pin LQFP All inputs have a weak internal pull-up circuit associated with them. These pull-up circuits are always enabled. Exceptions: 1. When owned by GPIO, then the pull-up may be disabled under software control. 2. TCK has a weak pull-down circuit always active. ...
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... Table 3. DSP56F826 Signal and Package Information for the 100 Pin LQFP All inputs have a weak internal pull-up circuit associated with them. These pull-up circuits are always enabled. Exceptions: 1. When owned by GPIO, then the pull-up may be disabled under software control. 2. TCK has a weak pull-down circuit always active. ...
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... Table 3. DSP56F826 Signal and Package Information for the 100 Pin LQFP All inputs have a weak internal pull-up circuit associated with them. These pull-up circuits are always enabled. Exceptions: 1. When owned by GPIO, then the pull-up may be disabled under software control. 2. TCK has a weak pull-down circuit always active. ...
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... Table 3. DSP56F826 Signal and Package Information for the 100 Pin LQFP All inputs have a weak internal pull-up circuit associated with them. These pull-up circuits are always enabled. Exceptions: 1. When owned by GPIO, then the pull-up may be disabled under software control. 2. TCK has a weak pull-down circuit always active. ...
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... Part 3 Specifications 3.1 General Characteristics The DSP56F826 is fabricated in high-density CMOS with 5-volt tolerant TTL-compatible digital inputs. The term 5-volt tolerant refers to the capability of an I/O pin, built on a 3.3V compatible process technology, to withstand a voltage up to 5.5V without damaging the device. Many systems have a mixture of devices designed for 3 ...
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... DMAX = =3.0 to 3.6V 2.25–2. DDIO DD DDA Symbol V IHC V ILC OZL DSP56F826 Preliminary Technical Data DC Electrical Characteristics Min Max Unit 2.25 2.75 3.0 3.6 –40 85 ° °C 1 100-pin LQFP Value Unit 39.7 °C/W User Determined ...
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... OZH OUT EIH POR = 8MHz); all inpuyts 0.2V from rail loads; osc DSP56F826 Preliminary Technical Data = – MHz Min Typ Max Unit -10 — – 0.7 — — DD — — 0.4 -300 — ...
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... V IL Section Pulse Width Low )/ Data2 Valid Data2 Data Tri-stated Figure 4. Signal States DSP56F826 Preliminary Technical Data AC Electrical Characteristics minimum of 2.0V for IH 3.2. In Figure 3 the levels of V High 90% 50% 10% Rise Time OH. and V OL OH. Data3 Valid Data3 ...
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... Table 9. IFREN Truth Table IFREN = 1 Read information block Program information block Erase information block Erase both block DSP56F826 Preliminary Technical Data ERASE MAS1 NVSTR IFREN = 0 ...
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... Program hold time Address/data set up time Address/data hold time Recovery time Cumulative program HV period Program time Erase time Mass erase time * The Flash interface unit provides registers for the control of these parameters. DSP56F826 Preliminary Technical Data Flash Memory Characteristics Symbol See Figure( ...
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... T nvh1 T — pgs T — rcv — DSP56F826 Preliminary Technical Data = – MHz Typ Max Unit — — us — — ms — — ms — — ...
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... IFREN XADR XE YADR YE DIN PROG Tnvs NVSTR Tpgs Figure 5. Flash Program Cycle IFREN XADR XE YE=SE=OE=MAS1=0 ERASE Tnvs NVSTR DSP56F826 Preliminary Technical Data Tadh Tads Tprog Thv Terase Figure 6. Flash Erase Cycle Flash Memory Characteristics Tpgh Tnvh Trcv Tnvh Trcv 23 ...
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... Tnvs NVSTR Figure 7. Flash Mass Erase Cycle 3.5 External Clock Operation The DSP56F826 system clock can be derived from a crystal or an external system clock signal. To generate a reference frequency using the internal oscillator, a reference crystal must be connected between the EXTAL and XTAL pins. 3.5.1 Crystal Oscillator ...
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... Figure 10. Connecting an External Clock Signal using EXTAL Crystal Frequency = 4MHz Sample External Crystal R Parameters DSP56F826 XTAL EXTAL V External SS Clock DSP56F826 XTAL EXTAL External No Connection Clock ( < 6MHz) DSP56F826 Preliminary Technical Data External Clock Operation Figure 9. The external clock source 25 ...
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... IL Table 13. PLL Timing = =3.0 to 3.6V 2.25–2. DDIO DD DDA Symbol Min 1 f osc — plls DSP56F826 Preliminary Technical Data = – MHz Typ Max Unit — 80 MHz — — — 3 — 90% ...
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... DOS (T*WS) + 6.4 t RDA t ARDD (T*WS) + 18.7 t DRD t RD (T*WS ARDA t RDD t WRRD t RDRD t WRWR t RDWR DSP56F826 Preliminary Technical Data External Bus Asynchronous Timing – MHz Unit Min Max 6.5 — 7.5 — — — 4.2 4.8 — 6.4 — — 0 — — ...
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... D0–D15 Note: During read-modify-write instructions and internal instructions, the address lines do not change state. Figure 12. External Bus Asynchronous Timing 28 t ARDD t ARDA t WRRD DOS DOH Data Out DSP56F826 Preliminary Technical Data t RDA t RDRD RDWR t RDD t DRD Data In ...
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... RAZ 275,000T 128T t 33T RDA t 1.5T IRW t IDM IRI IRQ t II DSP56F826 Preliminary Technical Data – Typical See Unit Max Figure — Figure 13 Figure 13 — ns — ns 34T ns Figure 13 — ns Figure 14 — ...
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... Figure 14. External Interrupt Timing (Negative-Edge-Sensitive) A0–A15, PS, DS, RD IDM IRQA, IRQB General Purpose I/O Pin t IG IRQA, IRQB Figure 15. External Level-Sensitive Interrupt Timing IRW First Interrupt Instruction Execution a) First Interrupt Instruction Execution b) General Purpose I/O DSP56F826 Preliminary Technical Data t RDA First Fetch First Fetch ...
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... Figure 18. Recovery from Stop State Using IRQA Interrupt Service Reset, Stop, Wait, Mode Select, and Interrupt Timing t IRI IRQ t II DSP56F826 Preliminary Technical Data First Interrupt Vector Instruction Fetch First Instruction Fetch Not IRQA Interrupt Vector First IRQA Interrupt Instruction Fetch 31 ...
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... Symbol ELD t ELG DSP56F826 Preliminary Technical Data 1 = – Min Max Unit See Figure Figures 19, 50 — ns 20, 21, 50 — ns Figure — — — ns Figure — ...
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... SS is held High on master MSB in Bits 14– Master MSB out Bits 14– DSP56F826 Preliminary Technical Data Serial Peripheral Interface (SPI) Timing LSB in t (ref Master LSB out ...
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... MSB in Bits 14– ELD Slave MSB out Bits 14– MSB in Bits 14–1 DSP56F826 Preliminary Technical Data ELG Slave LSB out LSB ELG ...
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... Figure 23. Quad Timer Timing Table 18. SCI Timing = =3.0 to 3.6V 2.25–2. DDIO DD DDA Symbol Min BR — RXD 0.965/BR PW TXD 0.965/BR PW DSP56F826 Preliminary Technical Data Quad Timer Timing – Min Max Unit 4T+6 — 2T+3 — 2T-3 — 1T-3 — ...
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... V, V =3.0 to 3.6V 2.25–2. DDIO DD DDA Symbol TRST t DE DSP56F826 Preliminary Technical Data – Min Max Unit DC 10 MHz 100 — 50 — 0.4 — 1.2 — — 26.6 — 23.5 50 — ...
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... TS TDO (Output ) t DV TDO (Output) Figure 27. Test Access Port Timing Diagram TRST (Input) t TRST Figure 28. TRST Timing Diagram Figure 29. OnCE—Debug Event DSP56F826 Preliminary Technical Data Input Data Valid Output Data Valid ...
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... A14 A13 A12 A11 A10 VSS VDD PIN 26 A0 EXTBOOT Figure 30. Top View, DSP56F826 100-pin LQFP Package 38 ORIENTATION MARK Motorola DSP56F826 DSP56F826 Preliminary Technical Data GPIOD1 GPIOD0 PIN 76 GPIOB7 GPIOB6 GPIOB5 GPIOB4 GPIOB3 GPIOB2 GPIOB1 GPIOB0 CLKO ...
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... Table 20. DSP56F826 Pin Identification by Pin Number Signal Pin No. Pin No. Name 1 TMS 26 2 TDI 27 3 TDO 28 4 TRST 29 5 VDDIO 30 6 VSSIO 31 7 A15 32 8 A14 33 9 A13 34 10 A12 35 11 A11 36 12 A10 ...
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... PLANE 0.100(0.004 0.20(0.008 T-U SECTION AE-AE CASE 842F-01 DSP56F826 Preliminary Technical Data NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DATUM PLANE -AB- IS LOCATED AT BOTTOM OF LEAD AND IS COINCIDENT WITH THE LEAD WHERE THE LEAD EXITS THE PLASTIC BODY AT THE BOTTOM OF THE PARTING LINE ...
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... C can be obtained from the equation For example, the user can change the air flow around CA do not satisfactorily answer whether the JA DSP56F826 Preliminary Technical Data Thermal Design Considerations 41 ...
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... CAUTION (GND) pin pairs, including DDA layers of the PCB with approximately 100 F, preferably with a high- DSP56F826 Preliminary Technical Data Electrical Design Considerations is the temperature of the package T – T )/P . This value gives pin on the DSP, and from DD /V SSA ...
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... Table 21. DSP56F803 Ordering Information Supply Part Voltage DSP56F826 3.0–3.6 V Plastic Quad Flat Pack (LQFP) 2.25-2. and V circuits Package Type Count DSP56F826 Preliminary Technical Data and V pins. DDA SSA Pin Frequency Order Number (MHz) 100 80 DSP56F803BU80 ...
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... ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; Silicon Harbour Centre, 2 Dai King Street, Tai Po Industrial Estate, Tao Po, N.T., Hong Kong. 852-26668334 Technical Information Center: 1-800-521-6274 HOME PAGE: http://motorola.com/semiconductors/dsp Æ are registered trademarks of Motorola, Inc. Motorola, Inc Equal MOTOROLA HOME PAGE: http://motorola.com/semiconductors/ DSP56F826/D ...