UPD16434 NEC, UPD16434 Datasheet

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UPD16434

Manufacturer Part Number
UPD16434
Description
1/8/ 1/16 DUTY LCD CONTROLLER/DRIVER
Manufacturer
NEC
Datasheet

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Document No. S10299EJ4V0DS00 (4th edition)
Date Published April 2000 NS CP(K)
Printed in Japan
DESCRIPTION
LCD and a microprocessor.
ASCII/JIS. Therefore, user original patterns can be easily displayed.
FEATURES
ORDERING INFORMATION
Note This package is only available in European market.
16-time-division 672 (42 by 16) dots
16-time-division n
160 characters
8-time-division 400 (50 by 8) dots
8-time-division n
DOT matrix LCD controller/driver
8- or 16-time division drive possible with a single chip
8- or 16-time division drive possible with no chip
Display data storage RAM 20
Programmer specified dot (graphic) display
Capable of alphanumeric and symbolic displays thorough built-in ROM (5 by 7 dots)
Parallel data input/output (Switch able between 4 and 8 bits)
Cursor manipulation command
Upgraded version of
PD16434 is LCD controller/driver containing the interfacing features for a dot-matrix mode 8-, 16-time division
PD16434G-xxx-12
PD16434G-001-12
PD16434GF-xxx-3B9
PD16434GF-001-3B9
Part Number
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
1/8, 1/16 DUTY LCD CONTROLLER/DRIVER
400 (50 by 8) dots
800 (50 by 16) dots
PD7228,
PD16434 contains a 5- by 7-dot matrix character generator corresponding to
80-PIN PLASTIC QFP (14 20)
80-PIN PLASTIC QFP (14 20), Standard ROM code
80-PIN PLASTIC QFP (14 20)
80-PIN PLASTIC QFP (14 20), Standard ROM code
50
PD7228A,
The mark
8 bits
PD7229,
DATA SHEET
shows major revised points.
Package
PD7229A
Note
MOS INTEGRATED CIRCUIT
Note
PD16434
1994, 1999

Related parts for UPD16434

UPD16434 Summary of contents

Page 1

... Note This package is only available in European market. The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. Not all devices/types available in every country. Please check with local NEC representative for availability and additional information. Document No. S10299EJ4V0DS00 (4th edition) ...

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PIN CONFIGURATION (Top View) PD16434G-xxx-12 80-PIN PLASTIC QFP (14 PD16434GF-xxx-3B9 80-PIN PLASTIC QFP ( C38 1 C39 2 C40 3 C41 4 C42/R15 5 ...

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R0/R8 to R7/R15 R8/C49 to R15/C42 8 R-S ROW DRIVER R- R-S LCD V LC1 R-NS V LC2 VOLTAGE C-S V LC3 CONTROL V LC4 C-NS V LC5 V SS LCD TIMING 16 SYNC CONTROL STOP SYSTEM ...

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PIN FUNCTIONS ……………………………………………………………………………………………… 1 (Data Bus) … 3-state input/output ……………………………………………….…………………..... 1.2 SI (Serial Data In) … Also serves as D0 input ……………………………………………………….………..… 1.3 SO (Serial Data Out) … Also serves as D3 output ………………………………….……………….…………. 1.4 P, ...

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Stopping Clock Supply and Retaining Data at Low Voltage in Standby Mode ………………………. 8. RESET OPERATION …………………………………………………………………………………….. 9. COMMANDS ……………………………………………………………………………………………… 9.1 LCD Display Mode Setting Commands ……………………………………………………………………... 9.2 Data Pointer Load Command …………………………………………………………………………………. 9.3 Data Processing Mode Setting Commands ...

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PIN FUNCTIONS 1 (Data Bus) … 3-state input/output In the parallel interface mode, these pins serve as 4-bit parallel data input/output pins. Data on the lines is read at the /STB signal rising ...

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Mode With chip address function - Always in parallel mode - When CAE = 1 in serial mode Without chip address function - When CAE = 0 in serial mode Remark In a multi-chip configuration in the serial interface mode, ...

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SYNC (Synchronous) … 3-state input/output In a multi-chip configuration, in which the row drive signal is commonly used, this pin inputs/outputs the synchronous signal in order to synchronize the phases of all LCD drive alternate cycle signals (row/column signals) ...

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C0 to C41 (Column) … Output These pins serve as LCD column drive signal output pins. 1.13 R8/C49 to R15/C42 (Row/Column) … Output These pins serve as LCD row drive signals R8 to R15 or column drive signals C49 ...

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INTERNAL BLOCK FUNCTIONS 2.1 Serial/Parallel Interface The PD16434 contains both serial and parallel interface functions. Whether the serial interface or the parallel interface is used is determined by whether the P, /S input is high (specifying the parallel interface) ...

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If the C, /D input indicates command specifications, the data input from the CPU to the serial/parallel interface is sent from the serial/parallel register to the command decoder for decoding. In the write mode, if the C, /D input indicates ...

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Figure 2–2. Character codes and Display Pattern (Standard ROM code: 001 Character code ...

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Figure 2–3 shows the LCD configuration for the character generator. A character is configured in 5 configuration. The most significant bit (bit 7) of the data memory is not used by the character generator. Therefore, LCD dots, corresponding to the ...

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Data Pointer The data pointer consists of a 6-bit binary counter (DP5 to DP0) and 1-bit bank flag (BNKF). It specifies the data memory address. BNKF The contents of the bank flag and the 6-bit binary counter are set ...

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Data Memory The data memory is a static RAM configured by two 50-word The data memory bank is specified by the bank flag in the data pointer, and the address in the bank is specified by the 6-bit binary ...

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Figure 2–6. Data Memory (8-Time-Division, Single/Multi-Chip) 31H bit C49 16 30H 01H 00H C48 column driver Data Sheet S10299EJ4V0DS00 PD16434 Corresponding ...

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Bank 0 and bank 1 are used in a pair, and the contents are read out to the column driver as 42 data. Figure 2–7 shows correspondence of bits for the row driver and column driver ...

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Bank 0 and bank 1 are used in a pair, and the contents are read out to the column driver as 50 data. The row driver signals, output from each Figure 2–8 shows bits correspondence for ...

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... This circuit generates the timing signals from the clock signal, according to the frame frequency specified by the SFF command, and the number of time divisions specified by the SMM command. The timing signals are necessary for automatically reading the display data and driving the LCD, and are supplied to the data memory row/column driver, and LCD voltage control circuit. ...

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Table 2–2. LCD Dual Mode Row Driver Function Selection Note 000 001 010 011 100 101 110 111 Notes Some other ...

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DATA INPUT/OUTPUT OPERATION In the PD16434, a command/data consists of 1 byte (8 bits), and processing is performed each time a byte of data is transferred in either the serial or parallel mode. The end of a byte data ...

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Figure 3–1. Serial Input Timing Waveforms (Without Chip Address Selection Function) /CS / SCK /BUSY Figure 3–2. Serial Output Timing Waveforms /CS /SCK SO /BUSY MSB MSB Data Sheet S10299EJ4V0DS00 PD16434 LSB Internal processing ...

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Hi-Z /BUSY /BUSY output for chip that was selected before /CS was set to high /BUSY output for selected chip Same chip 7th 8th MSB Chip address To all chips To newly selected chip /BUSY ...

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Hi-Z /BUSY /BUSY output for chip that was selected before /CS was set to high /BUSY output for selected chips 7th 8th Chip address To all chips MSB From newly selected chip /BUSY output ...

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Figure 3–5. Parallel Input Timing /CS /STB 1st Chip address CPU 16434 CPU 16434 C, /D /BUSY /BUSY output for newly selected chip /BUSY output for chip that was selected before /CS was set to high Data ...

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/BUSY Figure 3–6. Parallel Output Timing "L" 1st Upper Invalid Invalid data data 4 bits CPU 16434 16434 CPU CPU 16434 16434 CPU Data Sheet S10299EJ4V0DS00 PD16434 2nd Lower 4 bits Internal ...

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SELECTING PD16434 INTERFACE FUNCTION WITH CPU The command/data for the PD16434 is 8 bits long. However, serial interfacing with the CPU is made in 8-bit transfer or parallel interfacing is made in two 4-bit transfers. In addition, the selection ...

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... A, which has already been in the read mode to chip B, and again selecting chip A after that, the data pointer must be set by the data pointer load command reading data. 28 PD82C43 I/O expander. Therefore, the chip address PD82C43, when the Data Sheet S10299EJ4V0DS00 PD16434 PD50H is connected to the ...

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LCD DRIVE REFERENCE VOLTAGE SUPPLY The value of the LCD drive reference voltage to the divisions 16, so that the LCD drive reference voltage should be set as shown in Figure 5–1 and Figure 5–2. Figure ...

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... STOP mode or when it is being reset. Therefore, for a system to which reducing the current draw is extremely important, the current path thorough the resistor network must be cut off by an external circuit, when no displaying is performed, to eliminate unnecessary current flow. Figure 5–5 shows a circuit which cuts off the current to the resistor network during reset state (RESET = high) using the the RESET signal level instead of the V Figure 5– ...

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DISPLAY EXAMPLES Figure 6–1 shows how the data memory contents and LCD display pattern are corresponded, when displaying characters "AEZ" in 8-time-division mode. This example is to display 3 digits dot characters, and uses ...

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Figure 6–2. 8-Time-divisions (When Displaying Character LC1 ROW 0 V LC2 V LC3 V LC4 LC1 ROW 1 V LC2 V LC3 V LC4 LC1 ROW 7 V LC2 V ...

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Data memory address ...

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Figure 6–4. 16-Time-divisions (When Displaying Characters A and LC1 V LC2 ROW 0 V LC3 V LC4 V LC5 LC1 V LC2 ROW 1 V LC3 V LC4 V LC5 ...

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... Therefore, the standby mode is cleared, when writing the next 8-bit data is completed. Remark During the standby mode, the clock necessary for driving the LCD by alternating current is stopped. Therefore, the LCD drive signal level, before entering the standby mode, is maintained in the standby mode ...

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Figure 7–1. Controlling LCD Drive Voltage V DD CPU Output port Remark The power fed to the CPU and the (2) Clearing standby mode by RESET signal For a system for which only the contents of the data memory need ...

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Figure 7–2. CLOCK Supply Stop Timing Waveforms in Standby Mode STOP /BUSY /CS RESET CLOCK t SRC Data Sheet S10299EJ4V0DS00 Standby mode t HRC Data can be retained at a reduced voltage PD16434 37 ...

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RESET OPERATION The PD16434 is initialized as follows, when a high level is input to the RESET pin : The chip address compare data (compared with CA1, CA0 inputs) is initialized to 00 multi-chip configuration, /BUSY output ...

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If a RESET is executed during the standby mode, the standby mode is cleared. In this case, the data memory contents are retained. Figure 8–1. Example of /BUSY Output Timing Waveforms by RESET Input RESET /CS /BUSY Output from selected ...

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COMMANDS The PD16434 offers the following 16 different commands, each consisting of 1 byte (8 bits) : Mnemonic SFF Set Frame Frequency SMM Set Multiplexing Mode DISP OFF Display Off DISP ON Display On LDPI Load Data Pointer with ...

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Remark f : Clock frequency CL (2) SMM (Set Multiplexing Mode) 0 ...

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DISP OFF (Display Off This command sets the relationship of the row signal and column signal to non-select level, regardless of the display data, and deletes display. (4) DISP ON (Display On) 0 ...

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Automatically incremented (+1) each time a byte of data is processed Automatically decremented ( 1) each time a byte of data is processed This setting is not allowed ...

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The data pointer is then modified, according to I each time an 8-bit data is written by the ...

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Memory Bit Manipulation Commands The following four different memory bit manipulation commands are available: BRESET (Bit Reset) BSET (Bit Set) CLCURS (Clear Cursor) WRCURS (Write Cursor) The BRESET and BSET commands can be executed in any data processing mode. ...

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BRESET (Bit Reset This command or these commands resets (to 0) the bit specified by B the data pointer. Afterwards, the data pointer is modified according to J (2) BSET ...

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Standby Operation Setting Command (1) STOP (Set Stop Mode This command sets the STOP mode (standby mode). The data processing mode is initialized to the auto-increment (I Other modes are not affected by ...

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SYSTEM CONFIGURATION EXAMPLE Shows a circuit example, when four Figure 10–1. System Configuration Example (Multi-Chip C49 to C0 C49 to C0 CA1 (0) CA0 48 PD16434s are used in a multi-chip system configuration. LCD (40 characters ...

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ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings ( °C) A Parameter Symbol Power Supply Voltage V Note LCD Drive Voltage V LCD Input Voltage V Output Voltage V Operating Ambient Temperature T Storage Temperature T Note ...

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DC Characteristics – ° Parameter Symbol High Level Input Voltage Low Level Input Voltage High Level Input Leakage Current Low Level Input Leakage Current High Level Output Voltage Low Level Output Voltage ...

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AC Characteristics – 40 ° ° Common Operation Parameter Symbol Clock Operation Frequency Clock High Level pulse Width Clock Low Level pulse Width RESET High Level Width /CS /BUSY Delay Time /CS ...

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Parallel Input / Output Operation Parameter Symbol Command Input Set Time (/STB ) Command Input Hold Time (/STB ) Data Input Set Time (/STB ) Data Input Hold Time (/STB ) Data Output Delay Time Data Output Hold Time /STB ...

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DC Characteristics 2 (Unless otherwise specified, T Parameter Symbol High Level Input Voltage Low Level Input Voltage High Level Input Leakage Current Low Level Input Leakage Current High Level Output Voltage Low Level Output Voltage High Level Output Leakage Current ...

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AC Characteristics 2 (Unless Otherwise Specified, T Common Operation Parameter Symbol Clock Operation Frequency Clock High Level pulse Width Clock Low Level pulse Width RESET High Level Width /CS /BUSY Delay Time /CS /BUSY Float Delay Time t /CS High ...

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Parallel Input / Output Operation Parameter Symbol Command Input Set Time (/STB ) Command Input Hold Time (/STB ) Data Input Set Time (/STB ) Data Input Hold Time (/STB ) Data Output Delay Time Data Output Hold Time /STB ...

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AC timing measurement voltages (except /STB,/SCK, /BUSY) Clock timing waveforms CL RESET input timing waveforms RESET Interface specification timing waveforms RESET D1,D2 56 0 Test points 0 ...

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Serial input / output timing waveforms /CS t DCSB C, /D /BUSY t HBK /SCK SI SO Command/data specification t SDK t CYK t WHK 1st 2nd 8th t WLK t SIK t HKI Serial Serial data data (MSB) (LSB) ...

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Parallel input / output timing waveforms /CS t DCSB C, /D /BUSY /STB SDS t t HBS SH 1st 2nd Control Data input input ...

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Data Memory STOP Mode Low Power Supply Voltage Data Retention Characteristics (T Parameter Symbol Data Retention Power Supply V Voltage Data Retention Power Supply Current Data Retention High Level RESET V Input Voltage RESET, CLOCK Setup Time RESET, CLOCK Hold ...

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PACKAGE DRAWINGS PD16434G-xxx-12 80-PIN PLASTIC QFP (14x20 NOTE Each lead centerline is located within 0. its true position (T.P.) at maximum material condition ...

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PD16434GF-xxx-3B9 80-PIN PLASTIC QFP (14x20 NOTE Each lead centerline is located within 0. its true position (T.P.) at maximum material condition ...

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RECOMMENDED SOLDERING CONDITIONS When mounting the PD16434 by soldering should be performed under the following recommended conditions. Should other than recommended conditions be used, consult with our sales personnel. Surface Mount Type PD16434G-xxx-12 : 80-PIN PLASTIC QFP (14 PD16434GF-xxx-3B9: ...

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... HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction connection is provided to the input pins possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry ...

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... Specific: Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books. If customers intend to use NEC devices for applications other than those specified for Standard quality grade, they should contact an NEC sales representative in advance ...

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