UPD75218

Manufacturer Part NumberUPD75218
Description4-BIT SINGLE-CHIP MICROCOMPUTER
ManufacturerNEC
UPD75218 datasheet
 


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4-BIT SINGLE-CHIP MICROCOMPUTER
The PD75218 is a microcomputer with a CPU capable of 1-, 4-, and 8-bit-wise data processing, ROM, RAM,
I/O ports, an FIP controller/driver, a watch timer, a timer/pulse generator capable of outputting 14-bit PWM pulses,
a serial interface and a vectored interrupt function integrated on a single chip.
It is most suitable for applications which use fluorescent display tubes as display devices and require the timer/
watch function and high-speed interrupt servicing, such as VCR, CD and ECR. It can help to provide the unit with
many functions and to decrease performance costs.
The PD75218 has larger ROM and RAM capacity than its predecessor, PD75217. So several codes required
before have been reduced to only one code in the PD75218 specifications.
The one-time PROM product,
available for system development evaluation or small production.
The following manual provides detailed description of the functions of the PD75218. Be sure to read this manual
when you design an application system.
PD75218 User’s Manual: IEU-692
FEATURES
On-chip large-capacity ROM and RAM
• Program memory (ROM) : 32K
• Data memory (RAM)
: 1K
Architecture equal to that of an 8-bit microcomputer
High-speed operation: Minimum instruction execution time : 0.67 s (when the microcomputer operates at
6.0 MHz)
Instruction execution time variable function realizing a wide range of operating voltages
On-chip programmable fluorescent indication panel (FIP) controller/driver
Timer function : 4 ch
• 14-bit PWM output capability with the voltage synthesizer type electronic tuner
• Buzzer output capability
Interrupt function with importance attached to applications
• For power-off detection
• For reception of remote-controller signal
Product with an on-chip PROM :
Document No. IC-3035
Major changes in this version are indicated by stars ( ) in the margins.
(O. D. No. IP-8484)
Date Published November 1993 P
Printed in Japan
DATA SHEET
MOS INTEGRATED CIRCUIT
PD75P218 and various development tools (IE-75001-R, assembler, etc.) are
8 bits
4 bits
PD75P218 (on-chip EPROM : WQFN package)
The information in this document is subject to change without notice.
PD75218
© NEC Corporation 1993

UPD75218 Summary of contents

  • Page 1

    ... D. No. IP-8484) Date Published November 1993 P Printed in Japan DATA SHEET MOS INTEGRATED CIRCUIT PD75P218 and various development tools (IE-75001-R, assembler, etc.) are 8 bits 4 bits PD75P218 (on-chip EPROM : WQFN package) The information in this document is subject to change without notice. PD75218 © NEC Corporation 1993 ...

  • Page 2

    ... PD75218CW- PD75218GF- -3BE Remark is a ROM code. Please refer to "Quality Grades on NEC Semiconductor Devices" (Document number IEI-1209) published by NEC Corporation to know the specification of quality grade on the devices and its recommended applications LIST OF FUNCTIONS Item ROM: 32640 Built-in memory ® I/O line (including FIP ...

  • Page 3

    PIN CONFIGURATION (TOP VIEW) ......................................................................................... 2. BLOCK DIAGRAM ...................................................................................................................... 3. PIN FUNCTIONS ........................................................................................................................ 3.1 PORT PINS ...................................................................................................................................... 3.2 NON-PORT PINS ............................................................................................................................ 3.3 PIN INPUT/OUTPUT CIRCUIT LIST .............................................................................................. 3.4 HANDLING UNUSED PINS ........................................................................................................... 3.5 NOTES ON USE OF THE P00/INT4 ...

  • Page 4

    ELECTRICAL SPECIFICATIONS ............................................................................................... 13. CHARACTERISTIC CURVES (FOR REFERENCE) ..................................................................... 14. PACKAGE DIMENSIONS ........................................................................................................... 15. RECOMMENDED SOLDERING CONDITIONS ........................................................................ APPENDIX A FUNCTIONS OF PD752 APPENDIX B DEVELOPMENT TOOLS ......................................................................................... APPENDIX C RELATED DOCUMENTS ........................................................................................ 4 SERIES PRODUCTS ................................................ PD75218 42 ...

  • Page 5

    PIN CONFIGURATION (TOP VIEW P00/INT4 P01/SCK P02/SO P03/SI P10/INT0 P11/INT1 P12/INT2 P13/TI0 P20 P21 P22 P23/BUZ P30 P31 P32 P33 P60 P61 P62 P63 P40 P41 P42 P43 PPO ...

  • Page 6

    Basic interval timer Program counter (15) INTBT TI0/P13 Timer/event counter #0 INTT0 Timer/pulse generator PPO INTTPG SI/P03 Serial interface SO/P02 SCK/P01 INTSIO INT0/P10 INT1/P11 INT2/P12 Interrupt control INT4/P00 Watch timer BUZ/P23 ALU ROM Program memory 32640 8 bits Decode and ...

  • Page 7

    PIN FUNCTIONS 3.1 PORT PINS Dual- Pin I/O function pin P00 Input INT4 P01 Input/output SCK P02 Input/output SO P03 Input SI P10 INT0 Input P11 INT1 P12 INT2 P13 TI0 P20 Input/ ––– output P21 ––– P22 ––– ...

  • Page 8

    ... Edge-detected testable input (rising edge detection). Fixed frequency output (for buzzer or system clock trimming). Crystal/ceramic connection pin for main system clock oscillation. External clock input to X1 and its inverted clock input to X2. Crystal connection pin for subsystem clock oscillation. ...

  • Page 9

    PIN INPUT/OUTPUT CIRCUIT LIST Type P-ch IN N-ch CMOS-specified input buffer Type B IN Schmitt trigger input having hysteresis characteristics Type D V Data Output disable Push-pull output which can be set to high-impedance output (off ...

  • Page 10

    ... XT2 V when there is no on- LOAD chip load resistor 10 Recommended connection Connect Connect Connect Input state : Connect Output state : Leave open Leave open Connect Leave open Connect PD75218 ...

  • Page 11

    ... If the P50 pin signal is switched frequently between high and low, a spike is generated in the XT2 pin because of capacitance coupling of the P50 and XT2 pins and the correct watch functions cannot be achieved (the watch becomes fast necessary to allow the P50 pin signal to switch between high and low, mount an external capacitor to the P50 pin as shown below. XT1 is applied to one of these pins ...

  • Page 12

    MEMORY CONFIGURATION • Program memory (ROM): 32640 words • 0000H and 0001H: Vector table which contains the program start address after reset • 0002H to 000FH : Vector table which contains the program start addresses when interrupts occur • ...

  • Page 13

    MBE RBE Internal reset start address 0000H Internal reset start address 0002H MBE RBE INTBT/INT4 start address INTBT/INT4 start address 0004H MBE RBE INT0 start address INT0 start address 0006H MBE RBE INT1 start address INT1 start address 0008H MBE ...

  • Page 14

    Stack area Data area Static RAM (1024 4) 14 Fig. 4-2 Data Memory Map Data memory 000H General register (32 area 01FH 020H 256 0FFH 100H 256 1BFH 1C0H Display data (64 memory, etc. 1FFH 200H 256 2FFH 300H 256 ...

  • Page 15

    PERIPHERAL HARDWARE FUNCTIONS 5.1 PORTS The PD75218 has the following three types of I/O port: • 8 CMOS input pins (PORT0 and PORT1) • 20 CMOS I/O pins (PORT2, PORT3, PORT4, PORT5, and PORT6) • 4 P-ch open-drain output ...

  • Page 16

    CLOCK GENERATOR Operation of the clock generator is specified by the processor clock control register (PCC) and system clock control register (SCC). The main system clock or subsystem clock can be selected. The instruction execution time is variable. 0.67 ...

  • Page 17

    BASIC INTERVAL TIMER The basic interval timer has the following functions: • Interval timer operation to generate reference time • Watchdog timer application to detect inadvertent program loop • Wait time select and count upon standby mode release • ...

  • Page 18

    WATCH TIMER The PD75218 incorporates one channel of watch timer. The watch timer has the following functions: • Sets the test flag (IRQW) at 0.5 sec intervals. The standby mode can be released by IRQW. • 0.5 second interval ...

  • Page 19

    TIMER/EVENT COUNTER The PD75218 incorporates one channel of timer/event counter. The timer/event counter has the following functions: • Program interval timer operation • Event counter operation • Count state read function Fig. 5-4 Timer/Event Counter Block Diagram TMn7 TMn6 ...

  • Page 20

    ... Fixed time interval ( = 5.46 ms when the microcomputer operates at 6.0 MHz pulse output is not necessary, the PPO pin can be used as a 1-bit output port. Note 7.81 ms when the microcomputer operates at 4.19 MHz Caution If the STOP mode is set while the timer/pulse generator is in operation, erroneous operation may result. ...

  • Page 21

    Fig. 5-6 Timer/Pulse Generator Block Diagram (PWM Pulse Generation Mode) Modulo register H (8) TPGM3 MODH (8) TPGM1 f X 1/2 Frequency divider Note 7.81 ms when the microcomputer operates at 4.19 MHz. 5.7 SERIAL INTERFACE The serial interface has ...

  • Page 22

    P03/SI SIO0 Shift register (8) Note 1 P02/SO P01/SCK Notes 1. CMOS output and N-ch open-drain output switchable output buffer. 2. Instruction execution Fig 5-7 Serial Interface Block Diagram Internal bus 8 SIO7 SIO SIOM7 SIOM6 SIOM5 SIOM4 SIOM3 ...

  • Page 23

    FIP CONTROLLER/DRIVER The FIP controller/driver in the PD75218 has the same functions as that in its predecessor, PD75216A: • The FIP controller/driver outputs the segment signal by automatically reading display data (DMA operation) and automatically generates the digit signal. ...

  • Page 24

    INTERRUPT FUNCTIONS The PD75218 has eight types of interrupt sources and can generate multiple interrupts with priority order also equipped with two types of test sources. INT2 is an edge detected testable input. The PD75218 interrupt control ...

  • Page 25

    Fig. 6-1 Interrupt Control Circuit Block Diagram 2 2 IM1 IM0 Interrupt enable flag (IE INT IRQBT BT Both edges INT4/ detection IRQ4 P00 circuit Edge INT0/ detection IRQ0 Note P10 circuit Edge INT1/ IRQ1 Note detection P11 circuit INTSIO ...

  • Page 26

    STANDBY FUNCTIONS Two standby modes (STOP mode and HALT mode) are available for the PD75218 to decrease power consump- tion in the program standby mode. Table 7-1 Operation Status in Standby Mode Set instruction STOP instruction System clock when ...

  • Page 27

    RESET FUNCTIONS The reset signal (RES) generator has a configuration shown in Fig. 8-1. RESET Fig. 8-2 shows the reset operation. Fig. 8-2 Reset Operation by RESET Input RESET input Normal operation mode or standby mode Note 31.3 ms ...

  • Page 28

    Table 8-1 Hardware Statuses after Reset Operation Hardware Program counter (PC) PSW Carry flag (CY) Skip flag (SK0-SK2) Interrupt status flag (IST0, IST1) Bank enable flag (MBE, RBE) Stack pointer (SP) Stack bank selection register (SBS) Data memory (RAM) General ...

  • Page 29

    INSTRUCTION SET (1) Representation format and description method of operands An operand is described in the operand field of each instruction according to the description method corresponding to the operand representation format of the instruction (refer to "RA75X Assembler ...

  • Page 30

    Legend register, 4-bit accumulator register, 4-bit accumulator register, 4-bit accumulator register, 4-bit accumulator register, 4-bit accumulator register, 4-bit accumulator L : ...

  • Page 31

    Explanation of the symbols in the addressing area field * MBE•MBS (MBS = 15 MBE = (00H-7FH (80H-FFH) MBE = ...

  • Page 32

    Mnemonic Operand Instruction Transfer MOV A,#n4 reg1,#n4 XA,#n8 HL,#n8 rp2,#n8 A,@HL A,@HL+ A,@HL- A,@rpa1 XA,@HL @HL,A @HL,XA A,mem XA,mem mem,A mem,XA A,reg XA,rp’ reg1,A rp’1,XA XCH A,@HL A,@HL+ A,@HL- A,@rpa1 XA,@HL A,mem XA,mem A,reg1 XA,rp’ MOVT XA,@PCDE Table reference XA,@PCXA ...

  • Page 33

    Mnemonic Operand Instruction MOV1 CY,fmem.bit Bit transfer CY,pmem.@L CY,@H+mem.bit fmem.bit,CY pmem.@L,CY @H+mem.bit,CY ADDS A,#n4 Arithme- tic/logical XA,#n8 A,@HL XA,rp’ rp’1,XA ADDC A,@HL XA,rp’ rp’1,XA SUBS A,@HL XA,rp’ rp’1,XA SUBC A,@HL XA,rp’ rp’1,XA AND A,#n4 A,@HL XA,rp’ rp’1,XA OR A,#n4 A,@HL ...

  • Page 34

    Mnemonic Operand Instruction Increment/ INCS reg decrement rp1 @HL mem DECS reg rp’ SKE reg,#n4 Compari- son @HL,#n4 A,@HL XA,@HL A,reg XA,rp’ SET1 CY Carry flag manipula- CLR1 CY tion SKT CY NOT1 CY 34 Machine Number Operation of bytes ...

  • Page 35

    Mnemonic Operand Instruction SET1 mem.bit Memory bit fmem.bit manipula- pmem.@L tion @H+mem.bit CLR1 mem.bit fmem.bit pmem.@L @H+mem.bit SKT mem.bit fmem.bit pmem.@L @H+mem.bit SKF mem.bit fmem.bit pmem.@L @H+mem.bit SKTCLR fmem.bit pmem.@L @H+mem.bit AND1 CY,fmem.bit CY,pmem.@L CY,@H+mem.bit OR1 CY,fmem.bit CY,pmem.@L CY,@H+mem.bit XOR1 ...

  • Page 36

    Operand Mnemonic Instruction Subrou- CALL !addr tine stack control CALLA !addr1 CALLF !faddr RET RETS RETI PUSH rp BS POP rp BS Interrupt EI control Note IN A,PORTn I/O XA,PORTn Note OUT PORTn,A PORTn,XA Note MBE = ...

  • Page 37

    Operand Mnemonic Instruction HALT CPU control STOP NOP Special SEL RBn MBn Note GETI taddr Note The TBR and TCALL instructions are table definition assembler pseudo instructions of the GETI instructions. Machine Number Operation of bytes cycle 2 2 Set ...

  • Page 38

    MASK OPTION SELECTION The PD75218 has the following mask options enabling or disabling on-chip components. Pin P60 to P63 T0/T9 T10/S15/PH3 to T13/S12/PH0 T14/S11, T15/S10 XT1, XT2 Cautions system not using subsystem clocks, ...

  • Page 39

    APPLICATION BLOCK DIAGRAM 11.1 VCR TIMER TUNER Main power supply Power failure detection LPF Electronic tuner Tape count pulse Tape up/down SCK System controller SO microcomputer SI PD75104 or PD75106 EEPROM™ PD6252 PD6253 PD6254 + Super capacitor V V ...

  • Page 40

    COMPACT DISK PLAYER SIO SCK Servo SI/SO control IC Loading circuit BUZ T0–T13 14 Fluorescent indication panel (FIP) S0–S11 12 12 segments PD75218 Key matrix PORT6 (12 INT0 PC2800A X2 PD75218 14 digits 4) Remote-controller signal ...

  • Page 41

    ECR Main power supply Power failure detection RAM Printer + INT4 T0–T15 16 Fluorescent indication panel (FIP) S0–S9 10 PD75218 PPO XT1 XT2 PD75218 10 segments 16 digits Key matrix (10 4) ...

  • Page 42

    ELECTRICAL SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS ( Parameter Symbol V DD Power supply voltage V LOAD V PRE Input voltage Output voltage V OD Output high current I OH Output low current I ...

  • Page 43

    ... T In this example, the power consumption of 690 higher than the allowable total loss for the shrink DIP package (600 mW necessary to decrease power consumption by decreasing the number of on- chip pull-down resistors. In this example, power consumption can be adjusted to 577 incorporating pull-down resistors in only 11 digit outputs and 7 segment outputs and externally mounting pull-down resistors to the 2 remaining segment outputs ...

  • Page 44

    CHARACTERISTICS OF THE MAIN SYSTEM CLOCK OSCILLATOR (T Recommended Resonator constants Ceramic resonator X1 X2 Note Crystal resonator X1 X2 Note External clock X1 X2 PD74HCU04 Notes 1. The oscillator frequency and input frequency ...

  • Page 45

    CHARACTERISTICS OF THE SUBSYSTEM CLOCK OSCILLATOR (T Recommended Resonator constants Crystal Oscillator XT1 XT2 resonator frequency Note 3 (f 330 k Oscillation C3 C4 settling time Note XT1 input External frequency clock XT1 XT2 (f Leave open ...

  • Page 46

    RECOMMENDED PARAMETERS FOR THE OSCILLATION CIRCUIT When a ceramic resonator is used for the main system clock (T Manu- Product name facturer Murata CSA MG Mfg. CST MG CSA MG093 CST MGW093 CSA MGU CST MGWU CSA MG CST MGW ...

  • Page 47

    DC CHARACTERISTICS (Ta = – Parameter Symbol V Input high voltage IH1 V IH2 V IH3 V IH4 V Input low voltage IL1 V IL2 V IL3 Output high voltage V OH Output low voltage V ...

  • Page 48

    ... When the PCC register is set to 0000 and is operated in the low-speed mode. 5. When the system clock control register (SCC) is set to 1001 and is operated with the subsystem clock with main system clock oscillation stopped RD9. 1EL RD9. 1EL : Zener diode (NEC) Zener voltage = 8. –30 V PD75218 ...

  • Page 49

    ... INTL RESET low-level width t RSL Notes 1. CPU clock ( ) cycle time is determined by the oscillator frequency of the connected resona- tor, the system clock control register (SCC) and the processor clock control register (PCC). The cycle time t characteristics for power CY supply voltage V ...

  • Page 50

    AC Timing Measurement Values (Except X1 and XT1 Inputs) 0.75V 0.2V DD Clock Timing X1 input XT1 input TI0 Timing TI0 50 0.75V DD Test points 0. XTL XTH ...

  • Page 51

    Serial Transfer Timing SCK SI SO Interrupt Input Timing INT0, INT1, INT2 and INT4 RESET Input Timing RESET t KCY SIK KSI Input data t KSO Output data t t INTL INTH t RSL ...

  • Page 52

    DATA RETENTION CHARACTERISTICS FOR DATA MEMORY AT LOW SUPPLY VOLTAGE IN STOP MODE (Ta = –40 to +85 C) Parameter Symbol Data retention supply voltage V DDDR Data retention supply current Note 1 I DDDR Release signal set time t ...

  • Page 53

    CHARACTERISTIC CURVES (FOR REFERENCE) I 5000 1000 500 100 (Main system clock: 6.0 MHz Supply voltage V (V) DD PD75218 ( ...

  • Page 54

    I DD 5000 1000 500 100 (Main system clock: 4.19 MHz Crystal resonator 4.19 MHz Supply voltage V (V) DD PD75218 (T = ...

  • Page 55

    PACKAGE DIMENSIONS 64 PIN PLASTIC SHRINK DIP (750 mil NOTE 1) Each lead centerline is located within 0.17 mm (0.007 inch) of its true position (T.P.) at maximum material condition. 2) Item "K" ...

  • Page 56

    PIN PLASTIC QFP (14 20 NOTE Each lead centerline is located within 0.20 mm (0.008 inch) of its true position (T.P.) at maximum material condition. 56 detail of ...

  • Page 57

    ... Notice Other versions of the products are available. For these versions, the recommended reflow soldering conditions have been mitigated as follows: Higher peak temperature (235 C), two-stage, and longer exposure limit. Contact an NEC representative for details. 20 mm) Soldering conditions Note : 2 days ...

  • Page 58

    APPENDIX A FUNCTIONS OF PD752 Item ROM RAM Instruction When main cycle system clock is selected When sub-system clock is selected Total number of I/O lines I/O lines including FIP dual- CMOS input function lines pins and CMOS I/O lines ...

  • Page 59

    ... PA-75P216ACW PROM programmer adapter for the PD75P218CW. Connected to the PG-1500. PA-75P218GF PROM programmer adapter for the PD75P218GF. Connected to the PG-1500. PA-75P218KB PROM programmer adapter for the PD75P218KB. Connected to the PG-1500. Host machine IE control program • PC-9800 series (MS-DOS PG-1500 controller • IBM PC/AT ...

  • Page 60

    ... Package Manual SMD Surface Mount Technology Manual Quality Grades on NEC Semiconductor Devices NEC Semiconductor Device Reliability/Quality Control System Electrostatic Discharge (ESD) Test Guide to Quality Assurance for Semiconductor Devices Caution The above documents may be revised without notice. Use the latest versions when you design an application system ...

  • Page 61

    ... Strong static electricity may cause dielectric breakdown in gates. When transporting or storing MOS devices, use conductive trays, magazine cases, shock absorbers, or metal cases that NEC uses for packaging and shipping. Be sure to ground MOS devices during assembling. Do not allow MOS devices to stand on plastic plates or do not touch pins. ...

  • Page 62

    ... If customers intend to use NEC devices for above applications or they intend to use "Standard" quality grade NEC devices for applications not intended by NEC, please contact or they intend to use "Standard" quality grade NEC devices for applications not intended by NEC, please contact our sales people in advance ...