AN1139 STMicroelectronics, AN1139 Datasheet - Page 25

• Manufacturer Part Number: AN1139
• Description: L6254 - L6268 - L6269 12V DISK DRIVE POWER COMBO IC
• Manufacturer: STMicroelectronics

the programmed period. Any differences between the desired period and the pulse is the error in the transcon-
ductance loop and corrective action is taken by the charge pump.
The pulse measurement is initiated by an edge of the Feedback Frequency (Figure #10). If the feedback fre-
quency is higher than the reference frequency, then a DOWN pulse will be generated whose width is the differ-
ence in pulse width of the two inputs. If the feedback frequency is lower than the reference frequency than an
UP pulse will be generated whose width is the difference on pulse width of the inputs. The maximum pulse width
of the frequency comparator is set by the value programmed into the fine counter. UP and DOWN pulses control
the output of a current source or sink respectively which are connected to the FLL_FILTER pin (#21). The cur-
rent source and sink may also be turned on by the CPH and CPL bits in the serial port (Reg#8.6.7), however
these are mainly for testing purpose. The value of the source and sink currents is set by the ICP bit (Reg#8.1)
in the serial port. The result of this is a current pulse, whose width is proportional to the speed error, this is pre-
sented to the FLL_FILTER pin which is used with an external RC network to construct the Loop Filter for the
motor speed control. The FLL_FILTER pin is also internally connected to the input of a unity gain buffer. The
output of this buffer is clamped to a voltage set by ILO, IL1 and ISNS bits (Reg#8.3.4.5.) in the serial port. The
value for the clamp voltage are outlined in tables #2 and #4.
The coarse and fine counter arrangement is guaranteed to work in all possible circumstances. For example if
the zero crossing is within or outside the fine window or even if the zero crossing is in the coarse register range.
This system will even work if the zero crossing occurs across multiple coarse/fine cycles. The FLL has a pres-
caler (defined by the System Control Register bits MEC/ELEC and 8_12_POLE (Reg#2.5 & Reg#3.3) that
changes the cycle counting mechanism between electrical or mechanical (8 pole or 12 pole) i.e. dividing the
electrical period clock by 1, 4 or 6.
The equation for setting the Coarse and Fine Counters are calculated as shown in formulas #11 and #12 where
T0 is the period of the updating frequency that can be either electrical or mechanical and it is calculate as T0 =
60 / Rpm * Cycle. Cycle is the cycle counting mechanism and as explained before it can be 1,4 or 6 according
to desired cycle. Use 1 if Mechanical cycle is selected, use 4 or 6 if electrical cycle is chosen according to the
motor pole. Conventionally, 90% of T0 goes into the Coarse Counter, 10% goes into the Fine Counter. Rpm is
the desired speed.
The CoarseCounterPeriod is the time of one period of the Coarse Counter and it is equal to 1/Frequen-
cy(SYS_CLK) * 5 * 64. The FineCounterPeriod is the time of one period of Fine Counter and it is equal to 1/
Frequency(SYS_CLK) *5 *4. The CoarseCounterError is the error from the Coarse Counter calculation and
needs to be added to the FINE register calculation.
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•
Example whit a speed of 5400Rpm, Cycle=Mechanical and SYS_CLK=20MHz.
1. Calculate T0 reference period.
T0 = 60 / (Speed*Cycle) = 60 / (5400 *1) = 11 mS
2. Calculate Coarse Counter Period.
CoarseCounterPeriod = (1 / Frequency(SYS_CLK)) *5 * 64 = (1 / 20e6) * 5 * 64 = 16 S
3. Calculate Fine Counter Period.
FineCounterPeriod = (1 / Frequency(SYS_CLK)) *5 * 4 = (1 / 20e6) * 5 * 4 = 1 S
4. Calculate Coarse Register value.
11.
12.
COARSE_FREQ
COARSE_REG
=
=
----------------------------------------------------------------- -
C oar seCo unterPe rio d
-------------------------------------------------------------------------------------------- -
0.1 T0
Fine Cou nterPe riod
0.9 T0
+
Co arseC oun terErro r
FLL Coarse Counter
AN1139 APPLICATION NOTE
FLL Fine Counter]
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