AN1146 STMicroelectronics, AN1146 Datasheet
AN1146
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AN1146 Summary of contents
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... SDA bus low to acknowledge the receipt of the 8 bit data. A complete data transfer is always terminated by a STOP, identified by a low to high transition of the SDA line while the clock SCL is stable in the high state. 2 Fig Bus Protocol June 1999 AN1146 APPLICATION NOTE Authors: V. Marino, C. Vinci 1/14 ...
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... AN1146 - APPLICATION NOTE 3. Hardware Description The connection scheme between ST52x301 and EEPROM is shown in Figure 2. Pin P0 of ST52x301 is used to transfer data to and from the memory (SDA); pin P8 for data syncronization (SCL). In this scheme M24C04 inputs E0, E1 and E2 are tied to Vss (Device Select Code is A0h), therefore, being E0 low, only 256 byte of memory, the low part, can be addressed ...
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Random Address Read Mode In order to read a byte from an address of the memory, ST52x301 performs a dummy write to load the address, as shown in figure 4. Then, without sending a STOP condition, ST52x301 sends another ...
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... AN1146 - APPLICATION NOTE 4.1 Byte Write software routine The main flow chart program of ST52x301 Wryte Byte routine, as developed in FUZZYSTUDIO environment, is shown in Figure 5. After the block ‘ initialize ’, where the communication speed, the address and the value of the byte to write are set, the START condition is performed in the block ‘ start bit ’. ...
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This block performs the START condition: at first, the SDA line is pulled in high state through sending of the number ‘1’ into the parallel port (block ‘data_high’); then the SCL line is pulled high by setting ...
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... AN1146 - APPLICATION NOTE 4.1.4 ‘Ack’ block After sending 8 bits data, ST52x301 releases the SDA bus, setting the pin P0 in input. REG_CONF0 is used to set each pin of the parallel port in input or in output. During the 9-th clock pulse period, the EEPROM pulls the SDA bus low to acknowledge reception of the data byte: the byte read onto ST52x301 parallel port is stored into an ‘ ...
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A data transfer is always terminated by a STOP condition, that is identified by a low to high transition of the SDA line while the clock SCL is stable in the high state. This condition is performed ...
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... AN1146 - APPLICATION NOTE 4.2.1 ‘Read_data’ block To read the eigth bit data sent from the memory, ST52x301 performs a cycle scanned by a variable ‘ cont ’: at each step ‘cont’ is incremented from and one bit of the data is received into pin P0 (block ‘Receive0’) after the rising edge of the clock SCL (pin P8 of ST52x301). ...
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Appendix 1 Bit_byte Assembler Block This block is designated to write the data byte into the memory; the data is composed of eigth bits, then, in order to write it, a cycle of eight steps is realized (Fig.7). At the ...
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... AN1146 - APPLICATION NOTE 10/16 ...
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I C COMMUNICATION BETWEEN ST52x301 AND EEPROM 11/14 ...
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... AN1146 - APPLICATION NOTE Appendix 2 Bit_data Assembler Block This block is designated to read the data from the memory; the data is composed of eigth bits, then, in order to read it, a cycle of eigth step is realized(Fig.11). At the first step the cycle counter ‘ cont ’ is zero, then the intruction ‘ data-bit7 ’ is executed and the program jumps to label ‘ ...
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I C COMMUNICATION BETWEEN ST52x301 AND EEPROM 13/14 ...
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... AN1146 - APPLICATION NOTE Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specification mentioned in this publication are subject to change without notice ...