DS1085 Dallas Semiconductor, DS1085 Datasheet
DS1085
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DS1085 Summary of contents
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... DS1085Z-50 150mil SO DESCRIPTION The DS1085 is a dual-output frequency synthesizer requiring no external timing components for operation. It can be used as a standalone oscillator dynamically programmed, processor-controlled peripheral device. An internal master oscillator can be programmed from 66MHz to 133MHz with three resolution options of 10kHz, 25kHz, and 50kHz. A programmable, 3-bit prescaler (divide-by- permits the generation of a reference oscillator output (OUT0) from the master, ranging from 8 ...
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... Figure 1. DS1085 BLOCK DIAGRAM OVERVIEW A block diagram of the DS1085 is shown in Figure 1. The DS1085 consists of five major components: § Master oscillator control DAC § Internal master oscillator (66MHz to 133MHz) § Prescalers (divide-by- § ...
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... PART NUMBER DS1085Z-10 DS1085Z-25 DS1085Z-50 For further description of use of the OFFSET register, see the REGISTER FUNCTIONS section. The master clock can be routed directly to the outputs (OUT0 and OUT1) or through separate prescalers (P0 and P1). In the case of OUT1, an additional programmable divider (N) can be used to generate frequencies down to 8 ...
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Table 2. DEVICE MODE USING OUT0 EN0 SEL0 PDN0 (BIT) (BIT) (BIT *This mode is for applications where OUT0 is not used, ...
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... Correct operation of the device is not guaranteed for values of OFFSET not shown in Table 6. LSB MSB DS1085Z-25 Frequency DAC Offset 104.6MHz 600 Second Data Byte DS1085Z-50 Frequency DAC OS 101.8MHz 500 O2 O1 LSB X X Offset OS LSB O0 ...
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... EN0 0M1 0M0 DS1085Z-50 FREQUENCY RANGE — — — — 38.4 to 89.6 44.8 to 96.0 51.2 to 102.4 57.6 to 108.8 64.0 to 115.2 70.4 to 121.6 76.8 to 128.0 83.2 to 134.4 89.6 to 140.8 96.0 to 147.2 102.4 to 153.6 108.8 to 160.0 115 ...
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The functions of the individual bits are described in the following paragraphs. DIV1 (Default Setting = 0) This bit allows the output of the prescaler routed directly to the OUT1 pin (DIV1 = 1). In this condition, ...
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Table 7a. PRESCALER P0 DIVISOR M SETTINGS 0M1 0M0 PRESCALER *Factory Default Setting Table 7b. PRESCALER P1 DIVISOR M SETTINGS 1M1 1M0 PRESCALER P1 DIVISOR “M” ...
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N The DIV word sets the programmable divider. These 10 bits (N0–N9) determine the value of the programmable divider (N). The range of divisor values is from two to 1025, and is equal to the programmed value of N plus ...
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... COMMAND SET Data and control information is read from and written to the DS1085 in the format shown in Figure 3. To write to the DS1085, the master issues the slave address of the DS1085 and the R/ receiving an acknowledge, the bus master provides a command protocol. After receiving this protocol, the DS1085 issues an acknowledge, and then the master can send data to the DS1085 ...
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Access RANGE [37h the next data bytes read are the values stored in the RANGE register. This register has a 14- W bit value. The upper eight bits are sent first, followed by a second byte ...
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... The devices that are controlled by the master are “slaves.” A master device that generates the serial clock (SCL), controls the bus access, and generates the START and STOP conditions must control the bus. The DS1085 operates as a slave on the 2-wire bus. Connections to the bus are made through the open-drain I/O lines SDA and SCL. ...
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... Slave transmitter mode: The first byte is received and handled as in the slave receiver mode. However, in this mode, the direction bit indicates that the transfer direction is reversed. Serial data is transmitted on SDA by the DS1085 while the serial clock is input on SCL. START and STOP conditions are recognized as the beginning and end of a serial transfer. ...
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... A control byte is the first byte received following the START condition from the master device. The control byte consists of a 4-bit control code; for the DS1085, this is set as 1011 binary for read and write operations. The next three bits of the control byte are the device select bits (A2, A1, A0). The address bits to which the DS1085 responds are factory set to 000, but can be altered by writing new values to the ADDR register ...
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... Figure 4. 2-WIRE SERIAL COMMUNICATION WITH DS1085 ...
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ABSOLUTE MAXIMUM RATINGS* Voltage on Any Pin Relative to Ground Operating Temperature Range Storage Temperature Range Soldering Temperature * This is a stress rating only and functional operation of the device at these or any other conditions above those indicated ...
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MASTER OSCILLATOR CHARACTERISTICS PARAMETER SYMBOL Master Oscillator Range Default Master Oscillator Frequency Master Oscillator Frequency Tolerance Voltage Frequency Variation Temperature Frequency Variation Integral Nonlinearity of Frequency DAC AC ELECTRICAL CHARACTERISTICS PARAMETER SYMBOL Frequency Stable After DIV Change Frequency Stable After ...
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AC ELECTRICAL CHARACTERISTICS: 2-WIRE INTERFACE PARAMETER SYMBOL SCL Clock Frequency Bus Free Time Between a STOP and START Condition Hold Time (Repeated) START Condition LOW Period of SCL HIGH Period of SCL Setup Time for a Repeated START Data Hold ...
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This indicates the time taken between power-up and the outputs becoming active. An on-chip delay is intentionally introduced to allow the oscillator to stabilize. t clock cycles and hence depends on the programmed clock frequency. 10) Output voltage swings ...
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... DIVISOR (N) DS1085-25 DS1085- 4.75V 5.0V 5.25V 800 1000 ±5 0°C to +70°C SUPPLY CURRENT vs. VOLTAGE 30.0 25.0 20.0 15.0 DS1085-50 10.0 DS1085-25 DS1085-10 5.0 4.75 4.85 4.95 5.05 5.15 VOLTAGE (V) SUPPLY CURRENT vs. DIVISOR 200 400 600 800 DIVISOR (N) 5.25 70C 25C 0C 1000 ...
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... DIVISOR (N) FREQUENCY % CHANGE vs. SUPPLY VOLTAGE 2.0 1.5 1.0 0.5 0.0 -0.5 DS1085-50 -1.0 DS1085-25 -1.5 DS1085-10 -2.0 4.75 4.85 4.95 5.05 VOLTAGE (V) (V DS1085-50 DS1085-25 DS1085-10 800 1000 5.15 5. ± 5 0°C to +70°C SUPPLY CURRENT vs. DAC SETTING AND OFFSET ...