DS2148 Dallas Semiconducotr, DS2148 Datasheet - Page 12

• Manufacturer Part Number: DS2148
• Description: 5V E1/T1/J1 Line Interface
• Manufacturer: Dallas Semiconducotr

ACRONYM
RRING
TRING
(R/W*)
RCLK
RNEG
TNEG
LOTC
TCLK
(DS*)
RPOS
RTIP/
TPOS
TEST
TTIP/
RCL/
VSM
WR*
RD*
V
V
DD
SS
PIN
27/
34/
21/
22/
40
25
39
38
28
43
26
41
37
36
20
35
42
2
3
I/O
O
O
O
O
O
I
I
I
I
I
I
-
I
-
I
DESCRIPTION
Receive Clock. Buffered recovered clock from the line.
Synchronous to MCLK in absence of signal at RTIP and RRING.
Read Input (Data Strobe). RD* and DS* are active low signals.
DS active low when in nonmultiplexed, Motorola mode. See the Bus
Timing Diagrams in Section 12.
Receive Carrier Loss/Loss of Transmit Clock. An output which
will toggle high during a receive carrier loss (CCR2.7 = 0) or will
toggle high if the TCLK pin has not been toggled for 5msec ± 2msec
(CCR2.7 = 1). CCR2.7 defaults to logic 0 when in hardware mode.
Receive Negative Data. Updated on the rising edge (CCR2.0 = 0)
or the falling edge (CCR2.0 = 1) of RCLK with the bipolar data out
of the line interface. Set NRZE (CCR1.6) to a one for NRZ
applications. In NRZ mode, data will be output on RPOS while a
received error will cause a positive-going pulse synchronous with
RCLK at RNEG. See Section 8.4 for details.
Receive Positive Data. Updated on the rising edge (CCR2.0 = 0) or
the falling edge (CCR2.0 = 1) of RCLK with bipolar data out of the
line interface. Set NRZE (CCR1.6) to a one for NRZ applications. In
NRZ mode, data will be output on RPOS while a received error will
cause a positive-going pulse synchronous with RCLK at RNEG. See
Section 8.4 for details.
Receive Tip and Ring. Analog inputs for clock recovery circuitry.
These pins connect via a 1:1 transformer to the line. See Section 7
for details.
Transmit Clock. A 2.048MHz or 1.544MHz primary clock. Used to
clock data through the transmit side formatter. Can be sourced
internally by MCLK or RCLK. See Common Control Register 1 and
Figure 3-3.
3-state Control. Set high to 3-state all outputs and I/O pins
(including the parallel control port). Set low for normal operation.
Useful in board level testing.
Transmit Negative Data. Sampled on the falling edge (CCR2.1 =
0) or the rising edge (CCR2.1 = 1) of TCLK for data to be
transmitted out onto the line.
Transmit Positive Data. Sampled on the falling edge (CCR2.1 = 0)
or the rising edge (CCR2.1 = 1) of TCLK for data to be transmitted
out onto the line.
Transmit Tip and Ring [TTIP & TRING]. Analog line driver
outputs. These pins connect via a step-up transformer to the line. See
Section 7 for details.
Positive Supply. 5.0V ±5%
Voltage Supply Mode. Should be tied high for 5V operation
Signal Ground.
Write Input (Read/Write). WR* is an active low signal. See the
Bus Timing Diagrams in Section 12.
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