DS2148 Dallas Semiconducotr, DS2148 Datasheet - Page 14

• Manufacturer Part Number: DS2148
• Description: 5V E1/T1/J1 Line Interface
• Manufacturer: Dallas Semiconducotr

PIN DESCRIPTIONS IN SERIAL PORT MODE (Sorted by Pin Name, DS2148T
Pin Numbering) Table 4-3b
ACRONYM
BPCLK
HRST*
MCLK
RCLK
OCES
PBEO
LOTC
ICES
BIS0/
INT*
RCL/
BIS1
CS*
NA
PIN
32/
33
29
23
30
24
40
25
31
1
8
9
-
I/O
O
O
O
O
O
I
I
I
I
I
I
I
DESCRIPTION
Bus Interface Select Bits 0 & 1. Used to select bus interface option.
See Table 4-1 for details.
Back Plane Clock. A 16.384MHz, 8.192MHz, 4.096MHz, or
2.048MHz clock output that is referenced to RCLK selectable via
CCR5.7 and CCR5.6. In hardware mode, defaults to 16.384MHz
output.
Chip Select. Must be low to read or write to the device. CS* is an
active low signal.
Hardware Reset. Bringing HRST* low will reset the DS2148
setting all control bits to their default state of all zeros.
Input Clock Edge Select. Selects whether the serial port data input
(SDI) is sampled on rising (ICES =0) or falling edge (ICES = 1) of
SCLK.
Interrupt [INT*] pin 23. Flags host controller during conditions
and change of conditions defined in the Status Register. Active low,
open drain output.
Master Clock. A 2.048MHz (±50ppm) clock source with TTL
levels is applied at this pin. This clock is used internally for both
clock/data recovery and for jitter attenuation. Use of a T1 1.544MHz
clock source is optional.
See Note 1 on clock accuracy at the end of this table.
Not Assigned. Should be tied low.
Output Clock Edge Select. Selects whether the serial port data
output (SDO) is valid on the rising (OCES = 1) or falling edge
(OCES = 0) of SCLK.
PRBS Bit Error Output. The receiver will constantly search for a
2
Remains high if out of synchronization with the PRBS pattern.
Goes low when synchronized to the PRBS pattern. Any errors in the
received pattern after synchronization will cause a positive going
pulse (with same period as E1 or T1 clock) synchronous with
RCLK. PRBS bit errors can also be reported to the ECR1 and
ECR2 registers by setting CCR6.2 to a logic 1.
Receive Clock.
Synchronous to MCLK in absence of signal at RTIP and RRING.
Receive Carrier Loss / Loss of Transmit Clock. An output which
will toggle high during a receive carrier loss (CCR2.7 = 0) or will
toggle high if the TCLK pin has not been toggled for 5 msec ± 2
msec (CCR2.7 = 1). CCR2.7 defaults to logic 0 when in hardware
mode.
15
-1 or a 2
20
-1 PRBS depending on the ETS bit setting (CCR1.7).
14 of 75
Buffered recovered clock from the line.