DS2148 Dallas Semiconducotr, DS2148 Datasheet - Page 28

• Manufacturer Part Number: DS2148
• Description: 5V E1/T1/J1 Line Interface
• Manufacturer: Dallas Semiconducotr

6. CONTROL REGISTERS
CCR1 (00H): COMMON CONTROL REGISTER 1
(MSB)
ETS
SYMBOL
LOTCMC
JAMUX
RCLA
NRZE
ECUE
TTOR
TTOJ
ETS
NRZE
POSITION
CCR1.7
CCR1.6
CCR1.5
CCR1.4
CCR1.3
CCR1.2
CCR1.1
CCR1.0
RCLA
DESCRIPTION
E1/T1 Select.
0 = E1
1 = T1
NRZ Enable.
0 = Bipolar data at RPOS/RNEG and TPOS/TNEG
1 = NRZ data at RPOS and TPOS or TNEG; RNEG outputs a
positive going pulse when device receives a BPV, CV, or EXZ.
See figure 3-2 and figure 3-3.
Receive Carrier Loss Alternate Criteria.
0 = RCL declared upon 255 (E1) or 192 (T1) consecutive zeros
1 = RCL declared upon 2048 (E1) or 1544 (T1) consecutive
zeros
Error Counter Update Enable. A 0 to 1-transition forces the
next clock cycle to load the error counter registers with the
latest counts and reset the counters. The user must wait a
minimum of two clocks cycles (976ns for E1 and 1296ns for
T1) before reading the error count registers to allow for a proper
update. See Section 6 and figure 3-2 for details.
Jitter Attenuator MUX. Controls the source for JACLK. See
Figure 3-1.
0 = JACLK sourced from MCLK (2.048MHz or 1.544MHz at
MCLK)
1 = JACLK sourced from internal PLL (2.048MHz at MCLK)
TCLK to JACLK. Internally connects TCLK to JACLK. See
figure 3-3.
0 = disabled
1 = enabled
TCLK to RCLK. Internally connects TCLK to RCLK. See
figure 3-3.
0 = disabled
1 = enabled
Loss Of Transmit Clock Mux Control. Determines whether
the transmit logic should switch to JACLK if the TCLK input
should fail to transition. See figure 3-3.
0 = do not switch to JACLK if TCLK stops
1 = switch to JACLK if TCLK stops
ECUE
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JAMUX
TTOJ
TTOR
LOTCMC
(LSB)