DS2148 Dallas Semiconducotr, DS2148 Datasheet - Page 34

• Manufacturer Part Number: DS2148
• Description: 5V E1/T1/J1 Line Interface
• Manufacturer: Dallas Semiconducotr

INTERNAL RX TERMINATION SELECT Table 6-5
CCR6 (05H): COMMON CONTROL REGISTER 6
(MSB)
LLB
SYMBOL
ARLBE
(CCR5.1)
ALB
RLB
LLB
RT1
0
0
1
1
RLB
POSITION
CCR6.7
CCR6.6
CCR6.5
CCR6.4
ARLBE
(CCR5.0)
RT0
0
1
0
1
DESCRIPTION
Local Loopback. In Local Loopback (LLB), transmit data will
be looped back to the receive path passing through the jitter
attenuator if it is enabled. Data in the transmit path will act as
normal. See Figure 3-1 (DS2148 BLOCK DIAGRAM Figure
3-1 and section 8-2.2 for details.
0 = loopback disabled
1 = loopback enabled
Remote Loopback. In Remote Loopback (RLB), data output
from the clock/data recovery circuitry will be looped back to the
transmit path passing through the jitter attenuator if it is
enabled. Data in the receive path will act as normal while data
presented at TPOS and TNEG will be ignored. See Figure 3-1
(DS2148 BLOCK DIAGRAM Figure 3-1 and section 8-2.1 for
details.
0 = loopback disabled
1 = loopback enabled
Automatic Remote Loopback Enable and Reset. When this
bit is set high, the device will automatically go into remote
loopback when it detects loop-up code programmed into the
receive loop-up code definition registers (RUPCD1 and
RUPCD2) for a minimum of 5 seconds and it will also set the
RIR2.1 status bit. Once in a RLB state, it will remain in this
state until it has detected the loop code programmed into the
receive loop-down code definition registers (RDNCD1 and
RDNCD2) for a minimum of 5 seconds at which point it will
force the device out of RLB and clear RIR2.1. Toggling this bit
from a 1 to a 0 can reset the automatic RLB circuitry. The
action of the automatic remote loopback circuitry is logically
OR’ed with the RLB (CCR6.6) control bit (i.e., either one can
cause a RLB to occur).
Analog Loopback. In analog loopback (ALB), signals at TTIP
and TRING will be internally connected to RTIP and RRING.
The incoming signals, from the line, at RTIP and RRING will
be ignored. The signals at TTIP and TRING will be transmitted
as normal. See Figure 3-1 (DS2148 BLOCK DIAGRAM
ALB
Internal receive-side termination disabled
Internal receive-side 120W enabled
Internal receive-side 100W enabled
Internal receive-side 75W enabled
TERMINATION CONFIGURATION
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RJAB
INTERNAL RECEIVE
ECRS2
ECRS1
ECRS0
(LSB)