DS2164Q Dallas Semiconducotr, DS2164Q Datasheet - Page 4
DS2164Q
Manufacturer Part Number
DS2164Q
Description
G.726 ADPCM Processor
Manufacturer
Dallas Semiconducotr
Datasheet
1.DS2164Q.pdf
(17 pages)
- Current page: 4 of 17
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DS2164Q
Figure 1. BLOCK DIAGRAM
Figure 2. SERIAL PORT WRITE
Note: A 2-byte write is shown.
The bypass feature is enabled when BYP is set and IPD is cleared. During bypass, no expansion or
compression occurs. Bypass operates on bytewide (8 bits) slots when CP/
is set and on nibble-wide
EX
(4 bits) slots when CP/
is cleared.
EX
= 0) and m-law (U/
A-law (U/
= 1) PCM coding is independently selected for the X and Y channels
A
A
by CR.2. If BYP and IPD are cleared, then CP/
determines if the input data is to be compressed or
EX
expanded.
4 of 17
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