DS2182A

Manufacturer Part NumberDS2182A
DescriptionT1 Line Monitor
ManufacturerDallas Semiconducotr
DS2182A datasheet
 


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FEATURES
§ Performs framing and monitoring functions
Supports Superframe and Extended Super-
frame formats
§ Four onboard error counters
– 16-bit bipolar violation
– 8-bit CRC
– 8-bit OOF
– 8-bit frame bit error
§ Indication of the following
– yellow and blue alarms
– incoming B8ZS code words
– 8 and 16 zero strings
– change of frame alignment
– loss of sync
– carrier loss
§ Simple serial interface used for config-
uration, control and status monitoring
§ Burst mode allows quick access to counters
for status updates
§ Automatic counter reset feature
§ Single 5V supply; low-power CMOS tech-
nology
§ Available in 28-pin DIP and 28-pin PLCC
§ The DS2182A is upward-compatible from
the original DS2182
DESCRIPTION
The DS2182A T1 Line Monitor Chip is a monolithic CMOS device designed to monitor real-time
performance on T1 lines. The DS2182A frames to the data on the line, counts errors, and supplies
detailed information about the status and condition of the line. Large on-board counters allow the
accumulation of errors for extended periods, which permits a single CPU to monitor a number of T1
lines. Output clocks that are synchronized to the incoming data stream are provided for easy extraction of
S-Bits, FDL bits, signaling bits, and channel data. The DS2182A meets the requirements of ANSI
T1.231.
T1 Line Monitor
The updated DS2182A includes the following
changes from the original DS2182:
§ Ability to count excessive zeros
§ Severely Errored Framing Event indication
§ Updated AIS detection
§ Updated RCL detection
§ AIS and RCL alarm clear indications
PIN ASSIGNMENT
INT
1
SDI
2
SDO
3
CS
4
SCLK
5
NC
6
RYEL
7
RLINK
8
RLCLK
9
RCLK
10
RCHCLK
11
RSER
12
NC
13
VSS
14
28-Pin DIP (600-mil)
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DS2182A
28
VDD
27
RLOS
26
RFER
25
RBV
24
RCL
23
RNEG
22
RPOS
21
RST
20
TEST
19
RSIGSEL
18
RSIGFR
17
RABCD
16
RMSYNC
15
RFSYNC
092299

DS2182A Summary of contents

  • Page 1

    ... DESCRIPTION The DS2182A T1 Line Monitor Chip is a monolithic CMOS device designed to monitor real-time performance on T1 lines. The DS2182A frames to the data on the line, counts errors, and supplies detailed information about the status and condition of the line. Large on-board counters allow the accumulation of errors for extended periods, which permits a single CPU to monitor a number of T1 lines ...

  • Page 2

    ... DS2182A BLOCK DIAGRAM Figure DS2182A ...

  • Page 3

    ... If bipolar violation detected, low otherwise. Receive Frame Error. High during F-bit time when errors occur (193S), or when FPS or CRC errors occur (193E). Low during resync. Receive Loss of Sync. Indicates sync status; high when internal resync is in progress, low otherwise DESCRIPTION DS2182A ...

  • Page 4

    ... The port on the DS2182A can be read from or written to at any time. Serial port reads and writes are independent of T1 line timing signals RCLK, RPOS, and RNEG ...

  • Page 5

    ... The last bit of the address/ command word enables burst mode when set; the burst mode causes all registers to be consecutively read or written to. Data is read and written to the DS2182A LSB first. CHIP SELECT AND CLOCK CONTROL ...

  • Page 6

    ... SDO is updated on falling edge of SCLK. OPERATION OF THE COUNTERS All four of the counters in the DS2182A can be preset by the user to establish an event count interrupt threshold. The counters count up from the preset value until they reach saturation. At saturation, each additional event occurrence sets the appropriate bit in RSR2 and generates an interrupt if enabled by RIMR2 ...

  • Page 7

    ... CRC4 CRC3 NAME AND DESCRIPTION MSB of CRC6 word error count LSB of CRC6 word error count OOF4 OOF3 NAME AND DESCRIPTION MSB of OOF event count LSB of OOF of event count DS2182A LSB CRC2 CRC1 CRC0 LSB OOF2 OOF1 OOF0 ...

  • Page 8

    ... Receive Blue Alarm. Set when over window less zeros are received. Cleared when over window more zeros are received. Change of Frame Alignment. Set when the last resync resulted in a change of frame or multiframe alignment DS2182A LSB FE2 FE1 FE0 LSB ...

  • Page 9

    ... YELLOW ALARM 193S BIT 2. If RCR2 and RCR2 then the DS2182A examines bit 2 of all incoming channels for the presence of a yellow alarm. If bit 2 is set 256 consecutive channels, then the reception of a yellow alarm is declared. The alarm is considered cleared when the first channel with bit 2 set received ...

  • Page 10

    ... Receive Loss of Sync Mask interrupt enabled interrupt masked. B8ZS Code Word Detect Mask interrupt enabled interrupt masked. Receive Blue Alarm Mask interrupt enabled interrupt masked. Change of Frame Alignment Mask interrupt enabled interrupt masked DS2182A LSB B8ZSD RBL COFA ...

  • Page 11

    ... FECS NAME AND DESCRIPTION Severely Errored Framing Event Mask interrupt masked 1 = interrupt enabled Receive Carrier Loss Clear Mask interrupt masked 1 = interrupt enabled Receive Blue Alarm Clear Mask interrupt masked 1 = interrupt enabled DS2182A LSB OOFS CRCCS BPVCS LSB OOFS CRCCS BPVCS ...

  • Page 12

    ... FPS) in error Out Of Frame 2. OOF event description out of 6 frame bits (FT or FPS) in error 0 = follow OOF event described in RCR1.6 Auto Counter Reset. When set, all four of the counters will be reset to 0 when read DS2182A LSB SYNCT SYNCE RESYNC ...

  • Page 13

    ... F-bits before declaring sync. Sync Enable. If clear, the DS2182A automatically begins a resync if the conditions described in RCR1.7 are met. If set, no auto resync occurs. Resync. When toggled low to high, the DS2182A initiates a resync immediately. The bit must be cleared and set again for subsequent resyncs ...

  • Page 14

    ... In order to initiate another resync command, this bit must be cleared and then set again. RCR1.2=0 AVG. MAX. 3.75ms 4.5ms 7.5ms 9.0ms to initiate a resync resets the output timing while RST RCR1.2=1 MIN. AVG. 6.5ms 7.25ms 13.0ms 14.5ms is low; use RST DS2182A MAX 8.0ms 16.0ms RST ...

  • Page 15

    ... Superframe (193S or D4, 12 frames per Superframe). SF Yellow Mode Select the S-bit position of frame 12 bit 2 of all channels. Bipolar Eight Zero Substitution B8ZS enabled B8ZS disabled. Reserved; must be 0 for proper operation. Reserved; must be 0 for proper operation DS2182A LSB B8ZS - - ...

  • Page 16

    ... RLINK data (FDL data) is updated one bit-time prior to odd frames and held for two frames. RECEIVE MULTIFRAME BOUNDARY TIMING Figure 16 NOTES: 1. RLINK timing is shown for 193E; in 193S, RLINK is updated on even frame boundaries and is held across multiframe edges. 2. Total delay from RPOS and RNEG to RSER output is 13 RCLK periods DS2182A ...

  • Page 17

    ... RST Following reset, the host processor should restore all control modes by writing appropriate registers with control data. ALARM OUTPUT TIMING Figure 17 clears all registers and forces an immediate resync when DS2182A returns high. RST ...

  • Page 18

    ... Resync also occurs when loss of carrier is detected (RCL = 1) if RCR1 When RCR1 RLOS remains low until resync occurs, regardless of OOF or carrier loss flags. In this situation, resync is initiated only when RCR1.0 transitions low-to-high or the high. RST DS2182A pin transitions high-low- ...

  • Page 19

    ... -1.0 LO SYMBOL MIN TYP OUT MAX UNITS V +0 +0 ± 10%) DD MAX UNITS 3 mA +1.0 µ +1.0 µ MAX UNITS DS2182A NOTES NOTES 1 =25 C) NOTES ...

  • Page 20

    ... CHD 250 CL t 250 CCH t 2.5 CWH t CDV t CDZ = .8 and 10ns maximum rise and fall time ± 10%) DD TYP MAX UNITS 100 µs 200 DS2182A NOTES ...

  • Page 21

    ... PRD t TTR CCH t 50 SRD t 50 HRD t PRA t 1 RST = .8 and 10ns maximum rise and fall time 5.0V ± 10%) DD TYP MAX UNITS 648 ns 324 µs DS2182A NOTES ...

  • Page 22

    ... Data byte bits must be valid across low clock periods to prevent transients in operating modes. 2. Shaded regions indicate “don’t care” states of input. 1 SERIAL PORT READ AC TIMING DIAGRAM Figure 19 NOTES: 1. Serial port write must precede a port read to provide address information DS2182A ...

  • Page 23

    ... RECEIVE AC TIMING DIAGRAM Figure DS2182A ...

  • Page 24

    ... DS2182A T1 LINE MONITOR 28-PIN DIP INCHES DIM MIN. A 1.445 B 0.530 C 0.140 D 0.600 E 0.015 F 0.120 G 0.090 H 0.600 J 0.008 K 0.015 MAX. 1.470 0.550 0.160 0.625 0.040 0.145 0.110 0.680 0.012 0.022 DS2182A ...

  • Page 25

    ... DS2182AQ T1 LINE MONITOR 28-PIN PLCC INCHES DIM MIN. A 0.165 A1 0.090 A2 0.020 B 0.026 B1 0.013 C 0.009 D 0.485 D1 0.450 D2 0.390 E 0.485 E1 0.450 E2 0.390 L1 0.060 0.050 BSC CH1 0.042 MAX. 0.180 0.120 - 0.033 0.021 0.012 0.495 0.456 0.430 0.495 0.456 0.430 - - 0.048 DS2182A ...