DS2182A Dallas Semiconducotr, DS2182A Datasheet - Page 13

• Manufacturer Part Number: DS2182A
• Description: T1 Line Monitor
• Manufacturer: Dallas Semiconducotr

SYNCHRONIZER
The heart of the monitor is the receive synchronizer. This circuit serves two purposes: 1) monitors the
incoming data stream for loss of frame or multiframe alignment, and 2) searches for new frame alignment
pattern when sync loss is detected. When sync loss is detected, the synchronizer begins an off-line search
for the new alignment; all output timing signals remain at the old alignment with the exception of
RSIGFR, which is forced low during resync. When one and only one candidate is qualified, the output
timing moves to the new alignment at the beginning of the next multiframe. One frame later, RLOS will
transition low, indicating valid sync and the resumption of the normal sync monitoring mode. Several bits
in the RCR1 allow tailoring of the resync algorithm by the user. These bits are described below.
SYNC CRITERIA (RCR1.3)
193E. Bit RCR1.3 determines which sync algorithm is utilized when resync is in progress (RLOS = 1).
In 193E framing, when RCR1.3 = 0, the synchronizer will lock only to the FPS pattern and will move to
the new frame and multiframe alignment after the framing candidate is qualified. RLOS will go low one
frame after the move to the new alignment. When RCR1.3 = 1, the new alignment is further tested by a
CRC6 code match. RLOS will transition low after a CRC6 match occurs. If no CRC6 match occurs in
three attempts (three multiframes), the algorithm resets and a new search for the FPS pattern begins. It
takes 9 ms for the synchronizer to check the first CRC6 code after the new FPS alignment has been
loaded. Each additional CRC6 test takes 3 ms. Regardless of the state of RCR1.3, if more than one
candidate exists after 24 ms, the synchronizer begins eliminating emulators by testing their CRC6 codes
in order to find the true framing candidate.
193S. In 193S framing, when RCR1.3 = 1, the synchronizer cross-checks the FT pattern with the FS
pattern to help eliminate false framing candidates such as digital milliwatts. The FS patterns are
compared to the repeating pattern ...00111000111000...(00111x0 if RCR2.3 = 1). In this mode, FT and
FS must be correctly identified by the synchronizer before sync is declared. Clearing RCR1.3 causes the
synchronizer to search for the FT pattern (101010...) without cross-coupling the FS pattern. Frame sync
SYMBOL
RESYNC
SYNCC
SYNCT
SYNCE
POSITION
RCR1.3
RCR1.2
RCR1.1
RCR1.0
NAME AND DESCRIPTION
Sync Criteria. Determines the type of algorithm utilized by the
receive synchronizer; differs for each frame mode.
193S Framing (RCR2.4 = 0)
0 = synchronize to frame boundaries using FT pattern, then search
for multiframe by using FS.
1 = cross couple FT and FS patterns in sync algorithm.
193E Framing (RCR2.4 = 1)
0 = normal sync (utilizes FPS only).
1 = validate new alignment with CRC before declaring sync.
Sync Time.
1 = validate 24 consecutive F-bits before declaring sync.
0 = validate 10 consecutive F-bits before declaring sync.
Sync Enable. If clear, the DS2182A automatically begins a resync
if the conditions described in RCR1.7 are met. If set, no auto
resync occurs.
Resync. When toggled low to high, the DS2182A initiates a resync
immediately.
The bit must be cleared and set again for subsequent resyncs.
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DS2182A